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Autor Ghostrid3r

Sto su to L3 cache i TLB?

Tvoj omiljeni pretrazivac Interneta se rastepo ko Kirin pod pritiskom?

Ako te pak zanima sto se na tu temu dogadjalo konkretno u aemdeju ovih dana, baci oko na slijedece linkove

DailyTech - Understanding AMD's "TLB" Processor Bug
"How does the TLB erratum occur? All AMD quad-core processors utilize a shared L3 cache. In instances where the software utilizes nested memory pages, this processor will experience a race condition. "
http://www.dailytech.com/Understandi...rticle9915.htm

http://techreport.com/discussions.x/13721

http://techreport.com/discussions.x/13724

http://www.digitimes.com/mobos/a20071224PD200.html