Nadolazeći AMD socketi, ploče i procesori - Stranica 345

The Exiled · 29.03.2025., 16:12

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AMD Ryzen 9000G APUs for AM5 socket expected launch in Q4 2025

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AMD may be planning to introduce its next-gen APU series around Q4 2025. The obvious candidate for this upgrade is Strix Point, which would shift the Ryzen G-Series (Desktop APUs) from Zen 4 and RDNA 3 to Zen 5 and RDNA 3.5. Assuming it’s the Strix Point, these APUs would support the AM5 socket and would likely also enable AMD to launch the Ryzen 9000F series, budget-oriented models without integrated graphics. Such variants are popular among budget gaming prebuilt PCs. AMD's Ryzen 9000G "Strix" APUs family is supposedly the Strix Point variant of the laptop series, which was launched in the second half of 2024. Going by the specs' comparison of the Ryzen 8000 Phoenix Point mobile APUs and the Ryzen 8000G series for desktops, it appears that AMD might release up to a 12-core Ryzen 9000G processor.

Izvor: VideoCardz

The Exiled · 15.04.2025., 10:27

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AMD achieves first TSMC N2 product silicon milestone

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AMD today announced its next-generation AMD EPYC processor, codenamed "Venice," is the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2 nm (N2) process technology. This highlights the strength of AMD and TSMC semiconductor manufacturing partnership to co-optimize new design architectures with leading-edge process technology. It also marks a major step forward in the execution of the AMD data center CPU roadmap, with "Venice" on track to launch next year. AMD also announced the successful bring up and validation of its 5th Gen AMD EPYC CPU products at TSMC's new fabrication facility in Arizona, underscoring its commitment to U.S. manufacturing.

"TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing," said Dr. Lisa Su, chair and CEO, AMD. "Being a lead HPC customer for TSMC's N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing." "We are proud to have AMD be a lead HPC customer for our advanced 2 nm (N2) process technology and TSMC Arizona fab," said TSMC Chairman and CEO Dr. C.C. Wei. "By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing."

AMD's 6th Generation EPYC 'Venice' is expected to be based on the company's Zen 6 microarchitecture and is expected to be launched sometime in 2026. The CPU will rely on CCDs to be made on TSMC's N2 (2nm-class) fabrication process, so it is about time for the company to get the first Venice CCDs out of the fab. Yet, the fact that AMD already has chips it can talk about highlights the long-standing collaboration between AMD and TSMC as well as the culmination of joint efforts to build chips on one the most advanced process technologies that TSMC has ever developed to date. TSMC's N2 is the foundry's first process technology that relies on gate-all-around (GAA) nanosheet transistors. The company expects its manufacturing technology to offer either a 24% to 35% reduction in power consumption or a 15% increase in performance at constant voltage, along with a 1.15X boost in transistor density compared to the previous N3 (3nm-class) generation. These gains are primarily driven by the new type of transistors and the N2 NanoFlex design-technology co-optimization framework.

AMD's announcement comes after its arch-rival Intel delayed the release of its next-generation Xeon 'Clearwater Forest' processor made on its 18A manufacturing technology (which is set to rival TSMC's N2) to the first half of next year.

Izvor: TechPowerUp i Tom's Hardware

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TSMC unveils next-generation A14 process at North America Technology Symposium

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TSMC today unveiled its next cutting-edge logic process technology, A14, at the Company's North America Technology Symposium. Representing a significant advancement from TSMC's industry-leading N2 process, A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. Compared with the N2 process, which is about to enter volume production later this year, A14 will offer up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. Leveraging the Company's experience in design-technology co-optimization for nanosheet transistor, TSMC is also evolving its TSMC NanoFlex standard cell architecture to NanoFlex Pro, enabling greater performance, power efficiency and design flexibility.

The first iteration of 14A does not have backside power delivery. It was the same with N2 which was followed by A16 with Super Power Rail (SPR). SPR for A14 is expected in 2029. The TSMC 16A specs were updated as well. 16A is the first version of SPR for reduced IR drop and improved logic density. This has the transistor connection on the back. SPR is targeted at AI/HPC designs with improved signal routing and power delivery. A16 is on track for production in the second half of 2026. In comparison to N2P, A16 provides an 8-10% speed improvement at the same power, 15-20% power reduction at the same speed.

Izvor: TechPowerUp, SemiWiki, Bloomberg i Reuters

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TSMC is currently building at 24 factories worldwide + Next-Gen Packaging: TSMC to CoWoS, SoIC, SoW, HBM Base Dies, Optics and more

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There are figures and statistics that are unparalleled. The company illustrates how large TSMC is through the construction of 24 Fabs. This will enable the Group to consolidate its predominance in the field of contract manufacturing for other companies for decades. Years ago, every single factory construction was celebrated and TSMC's new construction project in the USA with three new factories also became a political event, but today individual fabs fade away when the overall picture is viewed at TSMC: 24 plants are currently under construction. 15 plants are currently being built in Taiwan, eleven wafer factories and four packaging facilities. The USA has caught up as a location through the last major investment with six factory buildings, all of which are phases of the Fab 21 in Arizona – the first already work – as well as two packaging facilities. A research campus is also located in the USA. In addition, there is a second factory in Japan and the plant in Germany.

By 2020, TSMC has built an average of three factories per year, and from 2021 to 2024, the average was raised to 5 fables per year. This year, the number has already climbed to nine falleries – eight wafer fabs and a packaging facility. Since the plants are built on average over three to four years, the large number of currently 24 simultaneous buildings come together. Packaging was another important topic at TSMC's 2025 Symposium. CoWoS-L, SoIC Gen 3 and innovations are coming to the fore. For increasingly complex types of chips, continuous improvements are also needed. These are realised together with the suitable new factory buildings. In production since 2021, CoWoS (Chips on Wafer on Substrate) has become a cash register hit. No modern larger chip is available without this technology. In the future, many of the possibilities mentioned will not be limited to servers, PCs, communication systems and smartphones, but will be extended in all directions.

Izvor: ComputerBase

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TSMC starts building US chip factory within hours of receiving permit – AMD CEO says 2nm HPC chips in play

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The Taiwan Semiconductor Manufacturing Company (TSMC) quietly broke ground at a third chip fabrication facility in Arizona yesterday, shared a press release by the Commerce Department. TSMC received the permit to start building the site yesterday and had construction equipment start working at the site within hours of receiving government approval. The ground breaking of a new factory follows a $100 billion commitment by the firm to invest in the US announced by President Trump earlier this year and is part of TSMC's Arizona campus, which kicked off construction under a previous $65 billion investment by the firm in the US.

TSMC's Arizona campus is the largest operating presence of the firm in the country. The firm's $65 billion initial investment had outlined three fabs, with the third final fab intended to produce advanced products on technologies such as the 2-nanometer node. TSMC broke ground on the third fab at the Arizona site yesterday, with Commerce Secretary Howard Lutnick visiting the site as soon as construction started. The primary goal of the Arizona fab is to provide US companies with their chip needs domestically instead of having to source the products from overseas, primarily Taiwan. Apple, nVidia and AMD's CEOs all shared their prepared remarks for the event.

AMD CEO Dr. Lisa Su went a step further and shared that her firm plans to use TSMC's N2 manufacturing process for high performance computing (HPC) applications. These chips are used in modeling, research, AI and other applications. Su shared that her firm is "a lead HPC customer for TSMC's N2 process and for TSMC Arizona Fab 21" and praised TSMC's technologies for enabling AMD to deliver advanced products.

Izvor: Bloomberg

The Exiled · 07.05.2025., 11:25

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Zen 5 architecture boosts AMD Client and Data Center sales

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AMD just wrapped up Q1 2025 with a strong showing thanks to its Zen 5 architecture. The company pulled in $7.44 billion in revenue, up 36 percent from this time last year, and net income jumped to $709 million from $123 million. That boost came from two main areas: client CPUs and data center chips. On the client side, Ryzen desktop and notebook processors generated $2.29 billion, a 68 percent increase over Q1 2024’s $1.37 billion. New parts like the Ryzen 7 9800X3D and 9 9950X3D helped, and AMD also scored a lot more OEM deals. In fact, major PC makers such as HP, Lenovo, Dell, and Asus are offering 80 percent more systems with Ryzen Pro than they did a year ago.

Over in the data center world, EPYC “Turin” chips are now shipping with all the big server vendors, and that lifted revenue from $2.36 billion to $3.67 billion. AMD also ran its first test wafers at TSMC’s new Arizona plant, using their N4 process. Those chips will start production in the U.S. later this year. Meanwhile, AMD and TSMC are testing the next-gen “Venice” silicon on the N2 node, aiming for a 2026 launch.

Not everything lit up the scoreboard, though. The gaming graphics group saw revenue slip 30 percent to $647 million, mainly because console-chip royalties dropped – even though the Radeon RX 9000 series launched. On the pro-GPU side, the Instinct accelerators are ready for prime time, but U.S. export controls are holding back the MI308 models bound for China unless AMD secures special licenses. That’s expected to shave about $700 million off Q2 and up to $1.5 billion over the full year. Despite that, AMD still anticipates double-digit growth in Instinct cards once licensing catches up.

Intense competition remains an ever-present challenge. In the crucial data center and AI market, Nvidia maintains a dominant market share, estimated at over 80%. While AMD’s Instinct accelerators like the MI300 series offer competitive hardware, its ROCm software ecosystem continues to work to bridge the gap with Nvidia’s deeply embedded CUDA platform. AMD has acknowledged this, describing its effort on ROCm as being in a “wartime stance” with a new sense of urgency. Intel also competes in data center CPUs and is developing its own AI accelerators. Intel remains a significant competitor in the Client segment, although AMD has made notable market share gains with its Ryzen processors.

In the decade since Su took the top job at AMD, the company has transformed itself into a leading provider of technology across the computing industry.
It now reports more than five times the revenue it had 10 years ago and is no longer in the shadow of Intel.

Izvor: Guru3D, ComputerBase, EE Times i Bloomberg

Dottore · 07.05.2025., 17:45

Trenutačno je jako slaba ponuda matičnih ploča sa 10Gbe LAN i škrtoj ponudi pcie x8. Uglavnom više manje odnosilo na B850m i x870 između 2,5 i 5Gbe. Prije sa AM4 x570 ATX verziji bili dostupni 10Gbe

The Exiled · 07.05.2025., 17:58

Modeli poput ProArt X670E-Creator Wi-Fi nude nativno 10GbE + 2.5GbE, ali ta ploča košta skoro 200€ skuplje, nego da kupiš npr. MSI Tomahawk X670E Wi-Fi i zasebnu PCI-E 10GbE karticu.

The Exiled · 13.06.2025., 00:14

AMD confirms next-gen EPYC Venice “Zen 6” CPUs with 256 cores in 2026, EPYC Verano “Zen 7” CPUs & Instinct MI500 GPUs for 2027
AMD says Instinct MI400X GPU is 10X faster than MI300X, will power Helios rack-scale system with EPYC 'Venice' CPUs
AMD announces MI350X and MI355X AI GPUs, claims up to 4X generational performance gain, 35X faster inference
AMD EPYC Venice boasts 256 cores and bandwidth galore — next-gen server CPUs arrive in 2026
AMD launches Instinct MI350 series, confirms MI400 in 2026 with 432GB HBM4 memory
AMD Instinct MI350: With up to 1,400 watts and new package against Goliath nVidia
AMD supercharges AI Data Centers with powerful MI350 GPU at Advancing AI 2025
From MI350 to MI500: AMD’s bold AI accelerator roadmap through 2027

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AMD manages to shift the dynamics of data center markets into its favour, server CPU market share now poised to match Intel by 2026. AMD manages to scale up to a 50% market share in the server CPU segment in less than a decade, credited to competitive EPYC CPUs. Interestingly, AMD's share in the server CPU market back in 2017 was zero percent, since the firm hadn't come up with competitive offerings at all. When the firm's CEO took over the office, AMD prioritized the workstation segment, coming up with the EPYC "Naples" series, which brought Zen architecture to the platform for the first time. Fast-forward a few years, and we see AMD gaining adoption at a much larger stage, mainly catalyzed by the EPYC lineups.

The Exiled · 04.07.2025., 12:55

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AMD Zen 6 could give X3D CPUs up to 240MB of cache

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AMD is seemingly capable of drastically increasing the cache capacity of its upcoming Zen 6 chips using stacked 3D V-Cache layers. AMD is reportedly bringing some big changes with its next-gen Zen 6 architecture, offering more cores and cache per CCD (Core Complex Die). The brand is seemingly capable of stacking its 3D V-Cache layers to boost the total available L3 pool, which could drastically boost performance in cache-sensitive tasks. Upcoming Ryzen CPUs are getting more exciting with each new rumour.

AMD has boosted the amount of cache on each 3D V-Cache layer to 96MB, up from 64MB on Zen 5. The brand is also planning a redesign of its chiplets, packing up to 12 cores inside each, giving access to up to 24 cores on consumer desktops and laptops. This should allow Team Red to offer single-CCD Ryzen CPUs with 144MB of L3 cache in total, comprised of 48MB (4MB per core) inside the CCD and 96MB on the 3D layer. On top of that, AMD is seemingly able to stack two of these 3D V-Cache layers, bringing the L3 total to 240MB (96 + 96 + 48). Note however, that these 2-Hi X3D variants may be exclusive to the professional segment (Threadripper / EPYC), especially if in-house testing doesn’t show a lot of benefits for regular users and gamers. What is sure according to the source, is that AMD is definitely capable of launching a gaming chip with 240MB of L3 cache. Perhaps the best option is to let users choose for themselves by launching regular Zen 6 processors alongside single and dual-layer 3D V-Cache variants.

Sources inside AMD have also indicated that the brand expects Zen 6 to deliver between 6% and 8% FP IPC (Floating Point Instructions Per Cycle) uplift compared to Zen 5. That said, this IPC isn’t final yet as it doesn’t take into account Zen 6’s gaming capabilities and PPC (Performance Per Clock) uplifts. The take here is that this FP IPC isn’t to be confused with the overall gen-to-gen improvement which is likely to be higher. Aside from these big changes, Zen 6 is also set to debut a new bridge-die interconnect which is said to reduce the latency of chiplet-to-chiplet communication, potentially enhancing it to a level where dual-CCD CPUs are no longer an issue for games. There will also be a new I/O die that could boost DDR5 support even higher. Considering all of this, Zen 6 is shaping up to be a great option for gamers, and we can’t wait to try it.

Izvor: Club386

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AMD sampling next-gen Ryzen desktop "Medusa Ridge," sees incremental IPC upgrade, new cIOD

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AMD is reportedly sampling its next-generation Ryzen desktop processor powered by the "Zen 6" microarchitecture, codenamed "Medusa Ridge," to close industry partners, such as platform designers and OEMs. The processor sees AMD update both the CCDs and client I/O die. AMD confirmed that it is building the "Zen 6" CCD on the TSMC N2 (2nm) node, which entered risk production earlier this year. The node is expected to be ready for mass-production of 2nm chips later this year. The 2nm node presents a significant jump in transistor densities from the current TSMC N4P node on which AMD builds its 8-core "Zen 5" CCD, that AMD will use to increase CPU core counts per CCD.

Sources point to the possibility of AMD increasing core counts per CCD to 12, and giving the CCD 48MB of L3 cache. At this point we don't know if all 12 cores will be arranged in a single CCX with a monolithic slab of 48 MB L3 cache, or if there's a dual-CCX layout with 6 cores per CCX sharing 24 MB of L3 cache, each. The other big upgrade with "Medusa Ridge" is its client I/O die (cIOD). AMD is expected to build its new generation cIOD on a newer EUV node such as 5nm N5 or 4nm N4P, a significant upgrade from the current 6nm N6. 1usmus says that the biggest reason for AMD to update its cIOD is the memory controller architecture. AMD is expected to give "Medusa Point" a new dual memory controller architecture. There are still two DDR5 channels per socket, but this is redesigned for increased memory speeds, letting AMD catch up with Intel in this area.

Izvor: TechPowerUp

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AMD Zen 6 targets 7GHz clock speeds

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Zen 6 marks one of AMD’s most aggressive generational leaps in recent history, the company is internally testing desktop CPUs that already reach 6.4GHz, with the ultimate performance target set “above 7 GHz.” These chips codenamed Olympic Ridge will be based on the N2X node, an enhanced version of TSMC’s 2 nm process, and represent a significant jump from the current Zen 4 lineup built on N4P. The move from N4P to N3P to N2P and finally to N2X spans three full node transitions. For comparison, AMD moved from Zen+ (12nm) to Zen 2 (7nm) and later to Zen 4 (5nm), with each step yielding substantial gains in efficiency and clock headroom. If successful, Olympic Ridge would exceed the 5.7GHz peak of Zen 4 and potentially outperform current top-end Intel Raptor Lake Refresh CPUs in single-threaded workloads.

However, it is important to note that this 7GHz target applies only to the desktop-class N2X-based variants. Most Zen 6 products, including the Medusa Point APU platform and Venice-class EPYC processors, will use the more mature N2P or N3P nodes. These parts may not match Olympic Ridge in raw frequency, but they are still expected to bring notable improvements in efficiency and performance-per-watt. AMD is likely concentrating its highest clocks on AM5 desktop SKUs and possibly a few select server models. Laptop-class APUs, such as Medusa Halo, are expected to top out at around 6.2 to 6.5GHz, still representing a 20% uplift over current-generation mobile parts. While clock speed alone does not determine overall performance, AMD’s attempt to break the 7 GHz barrier reflects its aggressive roadmap and willingness to adopt bleeding-edge manufacturing processes.

If achieved, a 7GHz Zen 6 desktop CPU would be the fastest clocked x86 processor ever released by AMD and potentially a landmark product in the desktop performance race. While final shipping frequencies are still unknown, internal testing and sourcing suggest AMD is on track to deliver a major leap with Olympic Ridge.

Izvor: Notebookcheck

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AMD CEO Lisa Su says US-made TSMC chips cost up to 20% more – but they're worth it

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AMD boss Lisa Su has confirmed something that we've been hearing for years now: buying chips from TSMC's US plants will be 5-20% more expensive than purchasing the same silicon from its Taiwan fabs. Su added that AMD expects its first chips from TSMC's Arizona facilities by the end of the year, and that the extra expense is worth it. Speaking in an interview with Bloomberg Television after her appearance at an AI event in Washington, Su highlighted the increased price of US-made TSMC chips compared to those from its Taiwan factories. It's no secret that building and running a cutting-edge fab costs more in the US, especially during the initial start-up period. People, concrete, permits, and the whole supporting ecosystem are pricier and less mature than in Taiwan, meaning a higher per-wafer cost.

Su says that paying the extra money is worth it as it means AMD is diversifying the crucial supply of chips. This will make the semiconductor industry less vulnerable to the type of disruption it experienced during the pandemic-induced chip crisis. "We have to consider resiliency in the supply chain," she said. "We learned that in the pandemic." Su also said that the yield rates of TSMC's Arizona plants were already comparable to its fabs in Taiwan. We heard back in January that TSMC's Arizona fab was already producing AMD Ryzen 9000 chips. The company also confirmed in April that the fifth-generation EPYC Turin chips had been "brought up and validated" in Phoenix, though volume shipments aren't expected until later this year.

Izvor: TechSpot

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AMD Ryzen 9000 CPU with 16 Zen5 cores, 192MB of L3 cache and 200W TDP reportedly on the way

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AMD is preparing to launch a Ryzen CPU based on the Zen 5 architecture with a higher TDP than current models and significantly larger L3 cache. According to the leak, two models are planned, both based on the Granite Ridge architecture (Zen 5) and featuring increased cache. The 8-core version is said to have a 120W TDP and 96MB of L3 cache. This configuration matches that of the Ryzen 7 9800X3D, suggesting it could be a lower-tier variant (possibly 9700X3D), which AMD typically releases later. More attention is on the 16-core version, reportedly featuring a 200W TDP, which is 30W higher than both the 9950X and 9950X3D. Importantly, it allegedly includes 192MB of L3 cache, indicating a dual CCD layout, each with 32MB standard cache and 64MB of 3D V-Cache. Reading between the lines, this suggests AMD may have decided, or is still evaluating, the possibility of launching its first desktop Ryzen CPU with dual 3D V-Cache dies. AMD previously stated that such configurations are expensive to produce, which is why they haven’t been released before.The current top model combines one CCD with 3D V-Cache and one without, requiring users to toggle between gaming and non-gaming modes, effectively disabling one chiplet during certain workloads.

Izvor: VideoCardz

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AMD’s next-gen AM6 socket to feature over 2100 pins, may support AM5 coolers

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Bits and Chips shared some interesting information from their sources. Apparently, despite increasing the pin count for AMD’s next-next-gen desktop CPUs, the socket size may remain similar enough to support existing coolers. According to the site, the total pin count will exceed 2100 pins (22% more than AM5). The socket is said to be similar in size and layout to the existing AM5 socket, which also suggests AMD is not moving away from its current LGA design. If you are aware of the recent developments around AMD's Zen 6 processors, you might know that it is expected to utilize the AM5 socket, extending the lifespan of the platform even further. AM6 reportedly launches in 2028 alongside Zen 7.

Izvor: Bits and Chips

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AMD posts record $7.685 billion revenue despite massive inventory charge

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AMD on Tuesday published its financial results for the second quarter of its fiscal 2025, posting revenue of $7.685 billion, which is its highest quarterly revenue ever. The company's results were driven by a significant uptick in client CPU sales and strong sales of its data center processors. But at the same time, the company's results were partially offset by the $800 million hit from Instinct MI308 GPU export restrictions to China. AMD's revenue for Q2 FY2025 reached $7.685 billion, marking a 32% year-over-year (YoY) and 3% quarter-over-quarter (QoQ) increase. The company's net income totaled $872 million, up 229% compared to the same quarter a year ago, and 23% sequentially. However, as a consequence of the $800 million writeoff, AMD's gross margin dropped to 40%, down from 49% YoY and from 50% QoQ.

For Q3 2025, AMD expects revenue of approximately $8.7 billion ± $300 million, representing around 28% year-over-year and 13% sequential growth at the midpoint, and another record quarter for AMD. This outlook reflects strong demand for AMD's AI accelerators as the company expects its Instinct MI350-series to ramp in Q3, EPYC server processors, and client products due to start of the back-to-school season and stockpiling for the upcoming Christmas season, though it excludes any potential revenue from Instinct MI308 GPU shipments to China, as export license applications remain under U.S. government review. While Q3 is traditionally good for AMD's gaming segment as console makers Microsoft and Sony increase purchases of SoCs for their products, this time around, AMD expects flattish revenue.

Izvor: Tom's Hardware

The Exiled · 03.09.2025., 19:05

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AMD Zen 6 processors to use TSMC 2nm node for CCDs, 3nm for IOD

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AMD will transition its next-generation "Zen 6" desktop Ryzen and server EPYC processors to a split-node strategy, placing CPU core complex die (CCD) on TSMC N2P 2nm node variant and building the I/O die (IOD) on the N3P 3nm node. At TSMC, volume ramp for the 2nm node is around the third quarter of 2026, opening the door for limited shipments as early as late Q3 or broader availability in Q4 2026. Under the split approach, the compute chiplet will house the Zen 6 cores and a substantially larger shared L3 pool, while the IOD will continue to host memory controllers, PCIe lanes, USB, and the integrated GPU.

With its next-generation I/O Dies, AMD plans to jump from TSMC’s N6 node to N3P. This means that AMD’s next-generation CPUs will leverage several node transitions to achieve a significantly larger-than-normal generational performance leap. Instead of benefitting from a single node shrink, AMD is jumping several generations ahead. For its CPU CCDs, AMD is jumping from TSMC N4 to N2P, skipping N3. With its I/O Dies, AMD is jumping from N6 to N3, skipping N5 and N4. Furthermore, AMD plans to use TSMC’s performance-optimised P-series nodes. Instead of N2 and N3, AMD is using N2P and N3P.

Earlier rumors suggest that each CCD could contain 12 Zen 6 cores with support for SMT, and a shared L3 cache that may increase to roughly 48 MB per CCD compared with prior generations. Typical consumer configurations would pair up to two CCDs with a single IOD, creating chips with up to 24 cores and 48 threads. Performance expectations center on achieving double-digit IPC gains, higher sustained clock speeds, and improved power efficiency, thanks to the advanced process nodes. The choice of N3P for IOD helps AMD cut some costs for non-core logic, while the N2P compute die aims to extract greater generational gains. However, as with any new TSMC node, it will carry a premium over the N3P, so using it only for the compute side is the most viable choice. Platform compatibility remains for one more generation, with Zen 6 expected to support the existing AM5 socket.

Izvor: TechPowerUp i OC3D

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AMD D2D interconnect in "Zen 6" gets Sea-of-Wires upgrade

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According to the High Yield YouTube channel, AMD is reportedly moving away from SERDES-based die-to-die links and toward a wide, parallel "sea-of-wires" routed through fan-out and RDL packaging, and the first hints of that change showed up in Strix Halo APU photos. The samples reveal a rectangular pad field where you would expect a fan-out, and the large SERDES block that used to sit at CCD edges is noticeably absent. That pattern, along with packaging choices consistent with TSMC's InFO-oS, suggests AMD is trying out dense parallel traces so fabric lanes can cross the package without being channeled into a few separate high-speed serial links. Usual serializing and deserializing data at every package boundary uses power and adds latency, thanks to clock recovery, equalization, and encoding and decoding overhead.

By moving to many short parallel wires, AMD can eliminate repeated PHY work and reduce round-trip delays, while allowing raw bandwidth to scale by adding physical lanes. The approach also frees the area that was once consumed by large SERDES blocks, which could let CCDs, memory controllers, and accelerators sit closer together with lower communication cost. There are real tradeoffs to solve, though. Packing lots of parallel traces under a die raises signal integrity, thermal, routing, and manufacturing challenges, so multi-layer RDL design and close co-engineering between die and package teams will be essential. If AMD can address those issues and carry the approach into Zen 6, we could see real per-watt and latency improvements for CPU workloads, including a faster memory IMC, thanks to lowered latency from the I/O die.

Izvor: TechPowerUp

The Exiled · 11.10.2025., 17:58

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AMD Zen 6 CPUs confirmed to work on existing AM5 motherboards

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Leaks have indicated that AMD intends to support the AM5 platform through at least the Zen 6 generation. Recent previews of upcoming motherboards from ASUS and ASRock offer the first concrete evidence that users with Zen 4 or Zen 5 CPUs can upgrade to Zen 6 without replacing their boards. AMD previously stated its plans to support the AM5 platform through at least 2027, though details about the company's next-generation CPUs remain limited. Earlier reports from prominent tipsters also suggested that Zen 6 would work with AM5 motherboards, but manufacturers had not confirmed the specifics until now.

Zen 6, slated for release in late 2026 or early 2027, is expected to build on Zen 5 with notable performance gains. Additional cores per chiplet will allow high-end Zen 6 CPUs to reach up to 24 cores and 48 threads, with L3 cache expanding to 48MB. Top-tier clock speeds may hit between 6.4GHz and 7GHz, surpassing Zen 4's 5.7GHz maximum. Beyond socketed CPUs, Zen 6 will power the next-generation Xbox and PlayStation consoles, with Microsoft's system featuring a 10-core APU. Laptop Zen 6 lineups, including Gator Rande and Medusa Point, may arrive in 2027, with the latter supporting the FP10 socket. Both utilize TSMC's N2P and N3P nodes, while flagship desktop Zen 6 processors will run on the more advanced N2X process.

Izvor: TechSpot

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Zen 6 CPUs will work on both 32MB and 64MB AM5 BIOS boards

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AMD’s next-generation Zen 6 CPUs are expected to work perfectly with existing AM5 motherboards, whether they have a 32 MB or 64 MB BIOS chip. The upcoming processors will be fully supported on all AM5 boards, covering the 600- and 800-series lineups like the B650, X670, B850, and X870. This reassurance comes shortly after ASUS unveiled its B850M AYM OC motherboard, which was the first board to officially list support for Zen 6. The model also featured a 64 MB BIOS, leading some users to wonder if only larger BIOS boards would be compatible.

That means owners of current-generation AM5 motherboards won’t need to replace their boards when Zen 6 launches. This is a big deal for users who invested early in AM5, as it keeps the upgrade path open without forcing new hardware purchases. It also shows that AMD learned from the compatibility issues it faced with AM4. Back then, 16 MB BIOS chips caused problems when trying to support too many generations of CPUs, forcing some motherboard makers to drop older models from their support lists. With AM5, AMD seems to have found a better balance, optimizing firmware to store all the necessary microcode for Zen 4, Zen 5, and now Zen 6.

If the leak turns out to be true, Zen 6 will be the third major CPU family on the AM5 socket, giving the platform a longer lifespan than many expected. It’s a strong signal that AMD intends to keep AM5 active for several more years—likely through at least 2027—before any major socket change. So, whether you own a mid-range B650 or a high-end X670E, you’ll probably be able to drop in a Zen 6 CPU without replacing anything else. That’s the kind of upgrade stability enthusiasts appreciate, especially when rival platforms tend to switch sockets more often.

While AMD hasn’t officially confirmed these details yet, the source behind the leak has a solid reputation for accuracy. If everything checks out, the Zen 6 launch will further strengthen AMD’s promise of long-term AM5 support, giving users more value and flexibility from their existing hardware.

Izvor: Guru3D

demetrius · 21.10.2025., 20:52

https://www.guru3d.com/story/previou...zen-7-9850x3d/

The Exiled · 05.11.2025., 13:42

Citiraj:

Još samo da se PR i marketing odjel fino raspusti u svezi glede Radeon driver podrške.

EDIT:

Citiraj:

Citiraj:

AMD's next-gen Zen 6 CPU ISA has been revealed in the latest support added to the GCC compiler, alongside the initial family. While AMD already offers AVX512 support on existing Zen architectures, AVX-512 FP16 will further boost the capabilities of future Zen architectures. The architecture will also support VNNI INT8 as part of its new ISA. Currently, Zen 6 is expected to feature the server Venice lineups in two variants, Classic & Dense. The Venice Classic chips have the SP7 "B50F00" SKUs, and the SP8 "B90F00" SKUs.

The Venice dense chips have the SP7 "BC0F00" SKUs, and the SP8 "BA0F00" SKUs. The classic line will feature up to 12 cores per CCX, while the dense line will feature 32 cores per CCX. We know that the Venice lineup will max out at 256 cores, so that's 8 CCXs, and each CCX carries 128 MB on the dense line, so we will get up to 1024 MB of L3 cache. All families with an MCM design will leverage the TSMC N2P process node, while monolithic offerings within the Medusa Point and Gator Range APU lines are expected to utilize TSMC N3P/N3C nodes.

Citiraj:

Microsoft is exploring ways to leverage the 'stack' of its AMD GPUs for inferencing workloads, as the company develops toolkits that convert nVidia CUDA models into ROCm-supported code. It is reported that the tech giant has developed 'toolkits' that allow the firm to run CUDA code on AMD GPUs by translating it into a ROCm-compatible version. We built some toolkits to help convert like CUDA models to ROCm so you could use it on an AMD, like a 300X. We have had a lot of inquiries about what is our path with AMD, the 400X and the 450X. We're actually working with AMD on that to see what we can do to maximize that.

AMD Zen 7 Grimlock Full Leak: 32-Core Specs & 448MB X3D Benchmarks!

07.05.2025., 17:45	#10324
Dottore Extrema Thule Moj komp Datum registracije: Feb 2005 Lokacija: 「 ✖ ✖ ✖ 」 Postovi: 7,675	Trenutačno je jako slaba ponuda matičnih ploča sa 10Gbe LAN i škrtoj ponudi pcie x8. Uglavnom više manje odnosilo na B850m i x870 između 2,5 i 5Gbe. Prije sa AM4 x570 ATX verziji bili dostupni 10Gbe __________________

07.05.2025., 17:58	#10325
The Exiled McG Moj komp Datum registracije: Feb 2014 Lokacija: Varaždin Postovi: 8,398	Modeli poput ProArt X670E-Creator Wi-Fi nude nativno 10GbE + 2.5GbE, ali ta ploča košta skoro 200€ skuplje, nego da kupiš npr. MSI Tomahawk X670E Wi-Fi i zasebnu PCI-E 10GbE karticu. __________________ AMD Ryzen 9 9950X \| Noctua NH-U12A chromax.black \| MSI MAG B650 Tomahawk Wi-Fi \| 128GB Kingston FURY Beast DDR5-5200 \| 256GB AData SX8200 Pro NVMe \| 2x4TB WD Red Plus \| Fractal Define 7 Compact \| Seasonic GX-750 AMD Ryzen 5 7600 \| Noctua NH-U12A chromax.black \| MSI MAG B650 Tomahawk Wi-Fi \| 128GB Kingston FURY Beast DDR5-5200 \| 256GB AData SX8200 Pro NVMe \| 2x12TB WD Red Plus \| Fractal Define 7 Compact \| eVGA 650 B5

21.10.2025., 20:52	#10330
demetrius Premium Moj komp Datum registracije: Jan 2005 Lokacija: rijeka Postovi: 3,869	https://www.guru3d.com/story/previou...zen-7-9850x3d/

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