[The Exiled]

Intel Foundry and ARM to collaborate on 1.8nm mobile SoCs

Arm and Intel Foundry Services on Wednesday announced plans to conduct design technology co-optimization (DTCO) and system technology co-optimization (STCO) for Arm's mobile IP on the Intel 18A fabrication technology (1.8nm-class). The plan will enable clients of Arm and IFS to maximize performance, lower power consumption, and optimize die sizes of their upcoming SoCs involving Arm's IP. Under the agreement, Intel Foundry Services and Arm will co-optimize Arm's IP and Intel's 18A fabrication process to increase the performance, power, area, and cost advantages of the new node. The two companies will initially focus on mobile SoC designs, but may eventually expand their collaboration to automotive, aerospace, datacenter, Internet of Things, and government applications. As part of the pact, Arm and IFS will develop reference design and optimized process developers kits for mobile SoCs.

When it comes to Intel's 18A fabrication process, there are a lot of things that can be optimized on node and design level to extract more PPAC advantages out of the node. One of the key innovations of Intel 18A is usage of gate-all-around (GAA) transistors that Intel calls RibbonFET. In GAA transistors, the channels are horizontally oriented and completely enclosed by gates. These GAA channels are created through epitaxy and selective material removal, enabling designers to fine-tune them by altering the transistor channels' width to get higher performance or lower power consumption. If everything works well, such control allows them to reduce transistor leakage current and performance variability — this provides great opportunities for DTCO.

Izvor: Tom's Hardware