[dh41400]

Autor Bubba

Ja sam bio uvjeren da ce taj novi CPU na S1150 donijeti (barem dio) AVX-512. Ali koliko vidim - qurchina.

Očito niti oni nisu bili sigurni da će im se to isplatiti na tom socketu, pa su sve prebacili na LGA 1151 (Skylake).

Dakle, ovo nas navodno čeka, na Skylake porodici:

• Direct Media Interface (DMI) 3.0
• Paralelna podrška za DDR4 i DDR3 RAM
• PCI Express 4.0 support na "-E" (extreme) verzijama procesora (~2017.),
• Thunderbolt 3.0
• SATA Express
• Iris Pro graphics (Direct3D 12.0)
• Eutanazija VGA sučelja i podrška za spajanje 5 monitora preko HDMI, DisplayPort i Embedded DisplayPort (eDP) sučelja
• Intel MPX (Memory Protection Extensions)
• Intel ADX (Multi-Precision Add-Carry Instruction Extensions)

Xeon Skylake inačice će također podržavati:

• Advanced Vector Extensions 3.2 ("AVX-512F")
• Intel SHA Extensions (SHA-1, SHA-256 Secure Hash Algorithms)

Ono što je zanimljivo da čak niti Skylake Xeon procesori neće imati potpunu AVX-512 podršku (samo 512F), već će značajnija podrška biti rezervirana za njihove Xeon Phi "Knights Landing" PCI Express add-in koprocesore.

Detaljnije:

AVX-512F, AVX-512 CDI, AVX-512 ERI, AVX-512 PFI

Introduced with Xeon Phi Knights Landing and Skylake Xeon, the first two (F and CD) together being known as AVX 3.1, with the last two (ERI and PFI) being specific to Knights Landing.

• AVX-512 Foundation – expands most 32-bit and 64-bit based AVX instructions with EVEX coding scheme to support 512-bit registers, operation masks, parameter broadcasting, and embedded rounding and exception control, supported by Knights Landing and Skylake Xeon
• AVX-512 Conflict Detection Instructions (CDI) – efficient conflict detection to allow more loops to be vectorized, supported by Knights Landing and Skylake Xeon
• AVX-512 Exponential and Reciprocal Instructions (ERI) – exponential and reciprocal operations designed to help implement transcendental operations, supported by Knights Landing
• AVX-512 Prefetch Instructions (PFI) – new prefetch capabilities, supported by Knights Landing

AVX-512 BW, AVX-512 DQ, AVX-512 VL

Introduced with Skylake Xeon, also known together with AVX-512F and AVX-512CD (AVX 3.1) as AVX 3.2.

• AVX-512 Byte and Word Instructions (BW) – extends AVX-512 to cover 8-bit and 16-bit integer operations
• AVX-512 Doubleword and Quadword Instructions (DQ) – adds new 32-bit and 64-bit AVX-512 instructions
• AVX-512 Vector Length Extensions (VL) – extends most AVX-512 operations to also operate on XMM (128-bit) and YMM (256-bit) registers