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The Exiled · 25.07.2023., 11:28

Citiraj:

Intel AVX10: Taking AVX-512 with more features & supporting it across P/E cores

Citiraj:

Intel posted its new APX (Advanced Performance Extensions) today and also disclosed the new AVX10 that will bring unified support for AVX-512 capabilities to both P-Cores and E-Cores for the first time. This evolution of the AVX instruction set will help Intel sidestep the severe issues it encountered with its new x86 hybrid architecture found in the Alder and Raptor Lake processors. Intel Advanced Vector Extensions 10 (AVX10) is a new ISA that includes "all the richness" of AVX-512 and additional features/capabilities while being able to work for both P and E cores. Intel says AVX10 will be "the vector ISA of choice" moving into the future. However, the new AVX10 ISA won't be supported with Intel's current-gen CPUs — it's slated to arrive in future chips. Intel says that AVX10 will be its vector ISA of choice moving into the future for both consumer and server processors.

AVX10 will allow Intel's chips that have both E-cores and P-cores to still support AVX-512, though 512-bit instructions can only run on P-cores. Meanwhile, converged 256-bit AVX10 instructions can run on either the p-cores or e-cores, thus allowing the full chip to still have support for AVX-512 capabilities. As such, Intel won't have to disable support for 512-bit vectors as it did when it disabled AVX-512 for both Alder Lake and Raptor Lake. However, the e-cores will be limited to the converged AVX10's maximum 256-bit vector length, while P-cores can use 512-bit vectors. This feels akin to Arm's support for variable vector widths with SVE. Intel says that existing applications will provide the same level of performance with AVX10 as they did with AVX-512, at least at the same vector lengths. To address developer feedback (obviously negative), Intel also plans to significantly simplify its AVX10 enumeration methods compared to AVX-512.

Intel also plans to ensure that each move to a new AVX10 revision has enough new instructions and capabilities to merit a change, thus reducing version and enumeration bloat.

Izvor: Phoronix i Tom's Hardware