@Dr. Strange
@ The Exiled
Citiraj:
On the new Zen3-based Ryzen 9 5950X, what immediately is obvious is that instead of four low-latency CPU clusters, there are now only two of them. This corresponds to AMD’s switch from four CCX’s for their 16-core predecessor, to only two such units on the new part, with the new CCX basically being the whole CCD this time around.
Inter-core latencies within the L3 lie in at 15-19ns, depending on the core pair. One aspect affecting the figures here are also the boost frequencies of that the core pairs can reach as we’re not fixing the chip to a set frequency. This is a large improvement in terms of latency over the 3950X, but given that in some firmware combinations, as well as on AMD’s Renoir mobile chip this is the expected normal latency behaviour, it doesn’t look that the new Zen3 part improves much in that regard, other than obviously of course enabling this latency over a greater pool of 8 cores within the CCD.
Inter-core latencies between cores in different CCDs still incurs a larger latency penalty of 79-80ns, which is somewhat to be expected as the new Ryzen 5000 parts don’t change the IOD design compared to the predecessor, and traffic would still have to go through the infinity fabric on it.
For workloads which are synchronisation heavy and are multi-threaded up to 8 primary threads, this is a great win for the new Zen3 CCD and L3 design. AMD’s new L3 complex in fact now offers better inter-core latencies and a flatter topology than Intel’s ring-based consumer designs, with SKUs such as the 10900K varying between 16.5-23ns inter-core latency. AMD still has a way to go to reduce inter-CCD latency, but maybe that something to address in the next generation design.
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Kao sto sam rekao chiplet dizajn je manjkav i ima tu jos puno posla da se latencije izmedu dva ccx-a dovedu na normalnu razinu. Iz teksta se vidi da su najveci pomak napravili sa latencija unutar jednog ccx-a (zapravo jednog monolith chipa), a izmedu dva chipleta su latencije i dalje ostale tragicne. Tak da sto god koristilo vise od 8 jezgri, a da nisu neke linearne radnje ce patiti.
TLDR chiplet dizajn je zaravo jedino dobar jer ti dopusta bolje yieldove, imas manje chipove od 4 i sad 8 jezgara i njih kombiniras kako ti pase. Medutim ogranicenja su i vise nego vidljiva.
@Madboy
Ovo je i odgovor na tvoju tvrdnju da "ne mogu napraviti niti 10nm, a gdje bi tek zavrsili da idu na chiplet". Kao sto vidis teze je sloziti takav monolitan chip, izazovi su veliki, a chiplet dizajn je samo manjkava alternativa.