[The Exiled]

Da, na kraju ispada da je ipak (malo) sporije, jer 3300X, 3900X i 3950X nisu, za razliku od ostale braće "razlomljeni" po istoj CCX/CCD osnovi, pa tu Infinity Fabric komunikacija baš i nema toliko negativan efekt, ako ga ima uopće. 3300X je direktno spojen na I/O jezgru, bez potrebe da preskače u prazno, dok su 3900X i 3950X ionak nafilani do kraja, mada istinabog 3900X je skraćen za jednu jezgru po CCX-u. Uglavnom, čuda tehnike, a Ryzen 4000 APU je najbolji primjer kak AMD slaže svoje Lego kockice, jer ti modeli imaju monolitan dizajn, bez zasebne I/O jezgre i s manjim 8M L3 cacheom, pa djeluju kao jedan ogroman CCD + iGPU, a performansama su u rangu ili malo bolji od tehnički jačih desktop varijanti.

On the Ryzen 3 3100, the four cores come from two different CCXes, which adds extra complexity to the latency structure. If a core in one CCX wants to communicate with the other CCX, it has to send a request out through the Infinity Fabric, which adds latency. This is called the ‘2+2’ configuration. Both designs are built with 16 MB of L3 cache, and with the 3300X that is all on one CCX, but split for the 3100. Because of the lower core count than the other Ryzen hardware, the effect of this split on the Ryzen 3 3100 is going to be more pronounced than others.

For Zen 2, a single chiplet is a core complex with 16 MB of L3. The reason the chiplet is so much smaller is that it doesn’t need memory controllers, it only has one IF link, and has no IO, because all of the platform requirements are on the IO die. This allows AMD to make the chiplets extremely compact. The IO die s also handling the memory controllers and what looks like power plane duties as well. There are no in-package links between the chiplets, in case anyone was still wondering: the chiplets have no way of direct communication – all communication between chiplets is handled through the IO die.

Izvor: AnandTech