Citiraj:
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I’ll add another word that is worth thinking about. AMD’s ThreadRipper uses a dual Zeppelin silicon, with each Zeppelin having two CCXes of four cores apiece. As observed in Ryzen, the cache-to-cache latency when a core needs data in other parts of the cache is not consistent. With Intel’s HCC silicon designs, if they are implementing a dual-ring bus design, also have similar issues due to the way that cores are grouped. For users that have heard of NUMA (non-unified memory access), it is a tricky thing to code for and even trickier to code well for, but all the software that supports NUMA is typically enterprise grade. With both of these designs coming into consumer, and next-to-zero NUMA code for consumer applications (including games), there might be a learning period in performance. Either that or we will see software pinning itself to particular groups of cores in order to evade the issue entirely.
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treba vidjeti kako ce intelov dual ring bus funkcionirati, infinity fabric bi tu mogao imati prednost.
intel ce vjerojatno za hcc cpu biti limitiran tdpom(pogotovo za 16/18c modele) sve iznad 3.4 GHz na svim jezgrama bilo bi iznenađenje, opet s druge strane amd ih tjera na iznenađenja