E6 - E4 Razlike ?

[ante2]

mozeli neko meni jednostavno reci u cemu je razlika izmedju dual core (i obicnih) AMD 64 procaova sa E6 i E4 revizijom jezge
evo link na AMD ove stranice za usporedbu
ja osim sta pise E6 i E4 ne vidim neku razliku
zna li ko meni objasniti u cemu je stos :confused:
www.amdcompare.com/us-en/desktop/Default.aspx

!"##$%$&/()=?= grom i pakao zasto se ova (gore navedena) www adresa ne pokazuje dobro
ispred tocke treba stajati (naravno) WWW

[Thoroughbred B]

Originally posted by ante2
mozeli neko meni jednostavno reci u cemu je razlika izmedju dual core (i obicnih) AMD 64 procaova sa E6 i E4 revizijom jezge
evo link na AMD ove stranice za usporedbu
ja osim sta pise E6 i E4 ne vidim neku razliku
zna li ko meni objasniti u cemu je stos :confused:
http://www.amdcompare.com/us-en/desk...=ADA3800DAA5BV

E3 i E6 je Venice a E4 je San Diego

Venice ima 512kb L2 kesha a San Diego 1MB L2 kesha

[ante2]

koliko ja vidim AMD 64X2 2800+(dual core) ima samo jednu varijantu sta se tice kesa tj samo sa 512KB x2 a ne sa 1024KB x2 :confused:
ali postoji verija E6 i E4 (obe imaju ist kolicinu kesa) e tu mene zanima u cemu je razlika

[Thoroughbred B]

Originally posted by ante2
koliko ja vidim AMD 64X2 2800+(dual core) ima samo jednu varijantu sta se tice kesa tj samo sa 512KB x2 a ne sa 1024KB x2 :confused:
ali postoji verija E6 i E4 (obe imaju ist kolicinu kesa) e tu mene zanima u cemu je razlika

Gore sam napisao za "obicne" razliku...Za dual core ne vrijedi to sto sam napisao,dual core su manchester i toledo jezgre,a za razliku manchester E4 i E6 nisam siguran

[Isus]

Razlika je u optimizacijam sse3 instruikcija, proizvodnom procesu tj. materijalima ( moraju odgovrata novim EU propisima za zastitu okolisa).

[ante2]

Originally posted by Isus
Razlika je u optimizacijam sse3 instruikcija, proizvodnom procesu tj. materijalima ( moraju odgovrata novim EU propisima za zastitu okolisa).

a koja je onda bolja verzija E6 ili E4 :confused:
po zdravoj logici E6 ili se varam i kako je prepoznat kada ti u ducanu daju kutiju sa procom :confused:

[Isus]

Za OC je bolji e3.
E6 je samo jod venicea druga revizija, kod San Diega ga nema.

E6 prepoznajes po zadnja dva slova BW .

Po svemu sto sam cu nema neke osjeten razlike izmedju E3 i E6.

E4 je samo oznaka E3 revizije s 1MB l2 cachea. znaci san diego

[mc_fish]

Originally posted by Isus
Razlika je u optimizacijam sse3 instruikcija, proizvodnom procesu tj. materijalima ( moraju odgovrata novim EU propisima za zastitu okolisa).

e3 ima olova u sebi ilitga bolje se kloka...dok e6 zbog zastite okolisa nema...razlika je 30mhz htt-a ilitga fsba

edit: isus ima bome oveca razlika...no opet je sve steping

[stiv haris]

da više razriješimo razliku između veničea e3 i e6.......
razlika je u 3 (tri) detaljčića odnosno greške kod e3 revizije koje su ispravljene u e6......
sve tri "greške" odnose se na integrirani memorijski kontroler......
kod AMD-a su detalji opisani u 3 točke:
113. Enhanced Write-Combining Feature Causes System Hang
Description
The enhanced write-combining feature provides up to four write-combining buffers, but a potential
stall condition can occur when write combining into all four buffers with this feature enabled.
Potential Effect on System
System hang.
Suggested Workaround
Disable the enhanced write-combining feature by setting BU_CFG.WbEnhWsbDis (bit 48 of MSR
C001_1023h). This reduces the number of available write-combining buffers from four to one.


114. DDR Data Pin Drive Strength Also Affects Command/Address
Pins
Description
Adjusting the drive strength of the DDR data pins by writing to the MemDQDrvStren field in the
DRAM Configuration High register (Dev:2x94[14:13]) also affects the drive strength of the
command/address pins.
Potential Effect on System
Adjusting the drive strength may cause unreliable operation of the DRAM interface.
Suggested Workaround
Do not adjust the DDR data pin drive strength settings in Dev:2x94[14:13]. BIOS should ensure that
these configuration bits remain at the default value of 00b.


116. DDR Chip Selects Tristated One Clock Early in Power Down
Mode
Description
When entering DDR Power Down mode with the Power Down Tristate feature enabled, the chip
selects are tristated coincident with the deassertion of the CKE pins, which is a violation of the DDR
specification.
Potential Effect on System
The DRAM enters an invalid state, resulting in unpredictable system operation. This applies only to
Power Down mode when the PwrDwnTriEn bit is set.
Suggested Workaround
Do not enable the Power Down Tristate feature. BIOS should ensure that Dev:2x90[7] remains at the
default value of 0b.


Izvor:Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors..........

[mc_fish]

Originally posted by stiv haris
da više razriješimo razliku između veničea e3 i e6.......
razlika je u 3 (tri) detaljčića odnosno greške kod e3 revizije koje su ispravljene u e6......
sve tri "greške" odnose se na integrirani memorijski kontroler......
kod AMD-a su detalji opisani u 3 točke:
113. Enhanced Write-Combining Feature Causes System Hang
Description
The enhanced write-combining feature provides up to four write-combining buffers, but a potential
stall condition can occur when write combining into all four buffers with this feature enabled.
Potential Effect on System
System hang.
Suggested Workaround
Disable the enhanced write-combining feature by setting BU_CFG.WbEnhWsbDis (bit 48 of MSR
C001_1023h). This reduces the number of available write-combining buffers from four to one.


114. DDR Data Pin Drive Strength Also Affects Command/Address
Pins
Description
Adjusting the drive strength of the DDR data pins by writing to the MemDQDrvStren field in the
DRAM Configuration High register (Dev:2x94[14:13]) also affects the drive strength of the
command/address pins.
Potential Effect on System
Adjusting the drive strength may cause unreliable operation of the DRAM interface.
Suggested Workaround
Do not adjust the DDR data pin drive strength settings in Dev:2x94[14:13]. BIOS should ensure that
these configuration bits remain at the default value of 00b.


116. DDR Chip Selects Tristated One Clock Early in Power Down
Mode
Description
When entering DDR Power Down mode with the Power Down Tristate feature enabled, the chip
selects are tristated coincident with the deassertion of the CKE pins, which is a violation of the DDR
specification.
Potential Effect on System
The DRAM enters an invalid state, resulting in unpredictable system operation. This applies only to
Power Down mode when the PwrDwnTriEn bit is set.
Suggested Workaround
Do not enable the Power Down Tristate feature. BIOS should ensure that Dev:2x90[7] remains at the
default value of 0b.


Izvor:Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors..........

to je dodatak razlog izvedbe u bezolovnom procesu je razlog e6-ice, da nije doslo do tog standarda...bila bi samo novija revizija iliti poboljsani e3, svejedno tnx 4 the info nisam ni znao da e6 imao poboljsani mem kontroler