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Datum registracije: Feb 2014
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AMD achieves first TSMC N2 product silicon milestone
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AMD today announced its next-generation AMD EPYC processor, codenamed "Venice," is the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2 nm (N2) process technology. This highlights the strength of AMD and TSMC semiconductor manufacturing partnership to co-optimize new design architectures with leading-edge process technology. It also marks a major step forward in the execution of the AMD data center CPU roadmap, with "Venice" on track to launch next year. AMD also announced the successful bring up and validation of its 5th Gen AMD EPYC CPU products at TSMC's new fabrication facility in Arizona, underscoring its commitment to U.S. manufacturing.
"TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing," said Dr. Lisa Su, chair and CEO, AMD. "Being a lead HPC customer for TSMC's N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing." "We are proud to have AMD be a lead HPC customer for our advanced 2 nm (N2) process technology and TSMC Arizona fab," said TSMC Chairman and CEO Dr. C.C. Wei. "By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing."
AMD's 6th Generation EPYC 'Venice' is expected to be based on the company's Zen 6 microarchitecture and is expected to be launched sometime in 2026. The CPU will rely on CCDs to be made on TSMC's N2 (2nm-class) fabrication process, so it is about time for the company to get the first Venice CCDs out of the fab. Yet, the fact that AMD already has chips it can talk about highlights the long-standing collaboration between AMD and TSMC as well as the culmination of joint efforts to build chips on one the most advanced process technologies that TSMC has ever developed to date. TSMC's N2 is the foundry's first process technology that relies on gate-all-around (GAA) nanosheet transistors. The company expects its manufacturing technology to offer either a 24% to 35% reduction in power consumption or a 15% increase in performance at constant voltage, along with a 1.15X boost in transistor density compared to the previous N3 (3nm-class) generation. These gains are primarily driven by the new type of transistors and the N2 NanoFlex design-technology co-optimization framework.
AMD's announcement comes after its arch-rival Intel delayed the release of its next-generation Xeon 'Clearwater Forest' processor made on its 18A manufacturing technology (which is set to rival TSMC's N2) to the first half of next year.
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Izvor: TechPowerUp i Tom's Hardware
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TSMC unveils next-generation A14 process at North America Technology Symposium
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TSMC today unveiled its next cutting-edge logic process technology, A14, at the Company's North America Technology Symposium. Representing a significant advancement from TSMC's industry-leading N2 process, A14 is designed to drive AI transformation forward by delivering faster computing and greater power efficiency. Compared with the N2 process, which is about to enter volume production later this year, A14 will offer up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, along with more than 20% increase in logic density. Leveraging the Company's experience in design-technology co-optimization for nanosheet transistor, TSMC is also evolving its TSMC NanoFlex standard cell architecture to NanoFlex Pro, enabling greater performance, power efficiency and design flexibility.
The first iteration of 14A does not have backside power delivery. It was the same with N2 which was followed by A16 with Super Power Rail (SPR). SPR for A14 is expected in 2029. The TSMC 16A specs were updated as well. 16A is the first version of SPR for reduced IR drop and improved logic density. This has the transistor connection on the back. SPR is targeted at AI/HPC designs with improved signal routing and power delivery. A16 is on track for production in the second half of 2026. In comparison to N2P, A16 provides an 8-10% speed improvement at the same power, 15-20% power reduction at the same speed.
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Izvor: TechPowerUp, SemiWiki, Bloomberg i Reuters
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TSMC is currently building at 24 factories worldwide + Next-Gen Packaging: TSMC to CoWoS, SoIC, SoW, HBM Base Dies, Optics and more 
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There are figures and statistics that are unparalleled. The company illustrates how large TSMC is through the construction of 24 Fabs. This will enable the Group to consolidate its predominance in the field of contract manufacturing for other companies for decades. Years ago, every single factory construction was celebrated and TSMC's new construction project in the USA with three new factories also became a political event, but today individual fabs fade away when the overall picture is viewed at TSMC: 24 plants are currently under construction. 15 plants are currently being built in Taiwan, eleven wafer factories and four packaging facilities. The USA has caught up as a location through the last major investment with six factory buildings, all of which are phases of the Fab 21 in Arizona – the first already work – as well as two packaging facilities. A research campus is also located in the USA. In addition, there is a second factory in Japan and the plant in Germany.
By 2020, TSMC has built an average of three factories per year, and from 2021 to 2024, the average was raised to 5 fables per year. This year, the number has already climbed to nine falleries – eight wafer fabs and a packaging facility. Since the plants are built on average over three to four years, the large number of currently 24 simultaneous buildings come together. Packaging was another important topic at TSMC's 2025 Symposium. CoWoS-L, SoIC Gen 3 and innovations are coming to the fore. For increasingly complex types of chips, continuous improvements are also needed. These are realised together with the suitable new factory buildings. In production since 2021, CoWoS (Chips on Wafer on Substrate) has become a cash register hit. No modern larger chip is available without this technology. In the future, many of the possibilities mentioned will not be limited to servers, PCs, communication systems and smartphones, but will be extended in all directions.
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Izvor: ComputerBase
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TSMC starts building US chip factory within hours of receiving permit – AMD CEO says 2nm HPC chips in play
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The Taiwan Semiconductor Manufacturing Company (TSMC) quietly broke ground at a third chip fabrication facility in Arizona yesterday, shared a press release by the Commerce Department. TSMC received the permit to start building the site yesterday and had construction equipment start working at the site within hours of receiving government approval. The ground breaking of a new factory follows a $100 billion commitment by the firm to invest in the US announced by President Trump earlier this year and is part of TSMC's Arizona campus, which kicked off construction under a previous $65 billion investment by the firm in the US.
TSMC's Arizona campus is the largest operating presence of the firm in the country. The firm's $65 billion initial investment had outlined three fabs, with the third final fab intended to produce advanced products on technologies such as the 2-nanometer node. TSMC broke ground on the third fab at the Arizona site yesterday, with Commerce Secretary Howard Lutnick visiting the site as soon as construction started. The primary goal of the Arizona fab is to provide US companies with their chip needs domestically instead of having to source the products from overseas, primarily Taiwan. Apple, nVidia and AMD's CEOs all shared their prepared remarks for the event.
AMD CEO Dr. Lisa Su went a step further and shared that her firm plans to use TSMC's N2 manufacturing process for high performance computing (HPC) applications. These chips are used in modeling, research, AI and other applications. Su shared that her firm is "a lead HPC customer for TSMC's N2 process and for TSMC Arizona Fab 21" and praised TSMC's technologies for enabling AMD to deliver advanced products.
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Izvor: Bloomberg
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Zadnje izmijenjeno od: The Exiled. 30.04.2025. u 12:45.
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29.03.2025., 15:12
