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Staro 18.11.2024., 20:43   #10291
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Staro 23.11.2024., 13:54   #10292
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AMD's future Ryzen SoCs may feature new chip-stacking technology
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AMD has recently filed a patent revealing plans to implement "multi-chip stacking" in future Ryzen SoCs. The patent details a new approach where smaller chiplets partially overlap with a larger die, creating space for additional components and functions on the same die. This strategy aims to improve the efficiency of the contact area, thus making room for higher core counts, larger caches, and increased memory bandwidth within the same die size. The proposed stacking will reduce the physical distance between components through overlapping chiplets, thus minimizing interconnect latency and achieving faster communication between different chip parts. The design will also improve power management, as the segregated chiplets allow for better control of each unit through power gating.

Even if long-time rival Intel has lost some of its momentum (and market share) this year, AMD's chance to push ahead with its intention to become number one in the market is to continue to innovate. In the same way that its 3D V-Cache technology made the X3D processor lineup so successful, this chip stacking approach could play a major role in future AMD Ryzen SoCs. It seems that AMD is committed to moving away from the monolithic design era and taking the road of multi-chiplet; however, it can be a long wait until (and if) this chip stacking will complete the journey from patents to design, production, and final product.
Izvor: TechPowerUp
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Staro 23.11.2024., 15:33   #10293
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Tako je, treba picit dalje kao Jensen, ne dopustit ko kurenciji ni da udahne… kao Intel.
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Staro 23.11.2024., 16:01   #10294
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Da, tak ispada, a Intel si je nažalost fino smjestil, dok ovi u AMD-u više ne znaju za mjeru, pa polako, ali sigurno sve moguće serverske ubojice fazana s vremenom dovode na desktop i HEDT.
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Intel was the first of the major CPU makers to add HBM stacked DRAM memory to a CPU package, with the “Sapphire Rapids” Max Series Xeon SP processors. But with the “Granite Rapids” Xeon 6, Intel abandoned the use of HBM memory in favor of what it would hope would be more main stream MCR DDR5 main memory, which has multiplexed ranks to boost bandwidth by nearly 2X over regular DDR5 memory. Importantly, the EPYC 9V64H has 128 GB of HBM3 memory that runs at a peak 5.2 GHz clock speed and that provides an aggregate of 5.3 TB/sec of peak memory bandwidth. A regular Genoa SP5 CPU socket using 4.8 GHz DDR5 memory delivers 460.8 GB/sec of bandwidth across a dozen DDR5 memory channels, by comparison. So this is a factor of 11.3X higher memory bandwidth across the same 96 cores of Genoa compute. By the way, the Xeon SP Max Series CPUs launched in November 2022 had four stacks of HBM2E memory with a total of 64 GB of capacity and in excess of 1 TB/sec of aggregate bandwidth out of that memory. AMD is delivering 71 percent more cores, 2X the memory capacity, and somewhere around 5X the memory bandwidth of the Intel CPU with HBM.
Izvor: The Next Platform
Uopće ne bi bilo čudno da s nadolazećim generacijama iskombiniraju 3D cache + HBM pod istim IHS-om, pa sve skupa zapakiraju za obične smrtnike.
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Staro 26.11.2024., 16:11   #10295
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AMD granted a glass substrate patent to revolutionize chip package — Intel, Samsung, and others racing to deploy the new tech
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AMD has been granted a patent that covers glass core substrate tech. Glass substrates will replace traditional organic substrates for multi-chiplet processors in the coming years. The patent not only means AMD has worked on appropriate technologies extensively but will enable the company to use glass substrates in the future without risks that a patent troll or competitors could sue it. Most chipmakers, including Intel and Samsung, are exploring glass substrates for future processors. Although AMD no longer produces its own chips, instead subcontracting them out to TSMC, it still has silicon and chip production research and development operations as the company customizes process technologies offered by its partners to build its products.

Glass substrates are made from materials like borosilicate, quartz, and fused silica, which provide notable benefits compared to traditional organic materials as they feature exceptional flatness, dimensional stability, and superior thermal and mechanical stability. Superior flatness and dimensional stability can improve lithography focus for ultra-dense interconnects in advanced system-in-packages, whereas superior thermal and mechanical stability makes them more reliable for high-temperature, heavy-duty applications like data center processors. One of the challenges when working with glass substrates is the implementation of Through Glass Vias (TGVs), according to the AMD patent. TGVs are vertical pathways created within the glass core to transmit data signals and power. Techniques such as laser drilling, wet etching, and magnetic self-assembly are utilized to produce these vias, but for now, laser drilling and magnetic self-assembly are fairly novel technologies.

Redistribution layers — which route signals and power between the chip and external components using high-density interconnections — are another integral component of advanced chip packages. Unlike main glass core substrates, these will continue to use organic dielectric materials and copper; only this time will they be constructed on one side of the glass wafer, requiring a new production method. The patent also describes a method for bonding multiple glass substrates using copper-based bonding (instead of traditional solder bumps) to ensure strong, gap-free connections. This approach enhances reliability and eliminates the need for underfill materials, making it suitable for stacking multiple substrates.

While AMD's patents clearly state that glass substrates offer such benefits as better thermal management, mechanical strength, and improved signal routing capabilities, which are advantages for data center processors, the patent implies that glass substrates could be applied to a variety of applications requiring high-density interconnections, including data center, mobile devices, computing systems, and even advanced sensors, which seems a bit overkill.
Izvor: Tom's Hardware
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Staro 28.11.2024., 11:26   #10296
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Ten years under Dr Su: How AMD went from budget Intel alternative to x86 contender
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In early 2014, with Rory Read at the helm, it had been a while since AMD had tasted glory. By Read's departure, the last time the company posed a real threat to Intel was back in the early 2000s with its Athlon 64 processors. After that point, the company slowly slid into position as the budget alternative for users who either couldn't justify or afford Intel's pricing.

By 2014, AMD's primary core architecture for desktop chips was codenamed Piledriver, a Bulldozer successor, but the only thing they are really remembered for is being power hungry and underperforming – on The Reg we once joked they could double up as portable space heaters. As for Intel's Sandy and Ivy Bridge chips, they were a design triumph that led to Chipzilla winning then maintaining dominance over the whole x86 market without breaking a sweat. And it wasn't seeing much pushback from AMD, whose lackluster architecture allowed Intel to dictate the direction of the desktop market. On top of this, AMD's revenues left a lot to be desired, its market share was even thinner, and it meant a long climb ahead if it wanted back in the game.

No one would have known this more than MIT engineer Dr Lisa Su, who was already AMD's chief operating officer running the company's sales and marketing teams. Named an IEEE Fellow in 2009, Su had been poached by AMD from Freescale Semiconductor, where she was CTO, in 2012. Su's appointment in 2014 tasked her with transforming not only AMD's overall narrative and public perception going forward, but also with defining a roadmap that was technically up to par. AMD needed to rebuild its core architectures from the ground up to have any hope of clawing back market share. Under her leadership, AMD shifted from the "affordable" alternative to a genuine contender. Ryzen put AMD back in the desktop market, EPYC began chipping away at Intel's datacenter dominance, and RDNA gave AMD's GPUs a second life. Today, AMD is no longer just the budget pick; it's setting the pace on price and performance, forcing Intel to keep up.

AMD spent the early 2010s struggling to stay relevant. Bulldozer, the CPU architecture it had pinned its hopes on, was supposed to keep AMD in the race with Intel. Instead, it became a case study on missed opportunities. Why? Bulldozer focused on core count at the expense of per-core performance, which backfired because most software still relied on single-threaded performance, Intel's area of strength. AMD's chips ran hot and simply couldn't compete on speed, leaving Intel to dominate the desktop CPU market on performance. Su didn't waste time when she took over as CEO in 2014. She binned the failing strategies and got AMD to work on a new roadmap that focused on solid engineering.

The result of all this was Zen, which we know today as AMD's Ryzen series. The original Zen microarchitecture launched in 2017, and it was a ground-up redesign focused on performance, efficiency, and scalability. It thrusted AMD back into the desktop game, but also became the foundation of AMD's key processors across all its primary product segments. Perhaps the biggest obstacle of the past ten years has been the graphics market, and despite significant improvements with both RDNA and RDNA 2, AMD still trails nVidia in performance. In areas such as ray tracing, AI-based upscaling, and general developer support, AMD still struggles to compete. nVidia's CUDA ecosystem has kept team green the dominant force in GPUs, especially in AI and gaming, which has kept AMD playing second fiddle despite competitive pricing and performance.

The biggest win for AMD of late is its market share in the server space, where formerly it had no presence whatsoever. Now it stands around 24 percent, a major improvement, and, with EPYC's dominance in core count compared to Intel, is sure to help push this even higher in the years to come. Su noted in the company's most recent earnings call for Q3 2024: "EPYC has become the CPU of choice for the modern datacenter and our multi-generation product portfolio delivers leadership performance and significant [total cost of ownership] advantages across virtually every enterprise and cloud workload."
Izvor: The Register
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Staro 28.11.2024., 12:51   #10297
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Kaže James Prior u zadnjem MLID podcastu, Intel ima playbook kako se izvući iz ove situacije - napisala ga je Lisa Su.
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Staro 28.11.2024., 13:00   #10298
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Još samo da netko ovom liku javi realno stanje stvari, pa nek spakira kofere i to je to.
Na pragu 2025. godine, ovaj biser priča o tome da bude Intel drugi najbolji do 2030.

I mene bude do onda Margot Robbie dočekala na kućnom pragu, jer eto, takve želje se ostvaruju, samo treba vjerovati.
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Staro 10.12.2024., 19:51   #10299
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AMD CEO Lisa Su named Time's CEO of the Year
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Advanced Micro Devices CEO Lisa Su has been recognized as CEO of the Year by Time Magazine, highlighting her transformative leadership over the past decade. When Su took the helm of AMD, the company's stock was trading at approximately $3, and its presence in the data-center chip market was negligible. Through a comprehensive redesign of AMD's products and improved customer relations, Su capitalized on the AI boom, propelling the company's value to surpass that of its historical rival, Intel, for the first time in 2022. AMD's stock has since soared to around $140.

Harvard Business School has also begun using Su's management of AMD as a case study, underscoring the significance of her achievements in turning around the semiconductor firm. Despite these successes, AMD remains second in the semiconductor industry, behind nVidia, which has become the most valuable company globally under the leadership of Su's cousin, Jensen Huang. nVidia has dominated the AI data-center GPU market, with a 95% share in the third quarter of 2024.
Iako je u pitanju većinom video PR materijal, Lisa Su čak i sad kad na srebernom pladnju ima serviranu priliku, ipak ne ide putem koji je odabral Pat Gelsinger, tj. ne omalovažava konkurenciju, dok u prvom licu u superlativima priča o kojekakvim retrovizorima. Uopće ne sumnjam da će Harvard i za Gelsingera složiti zasebno istraživanje i popratno predavanje na temu vođenja firme, samo bude naglasak na malo drugačijim lekcijama i potezima od onih koje je Lisa Su implementirala.
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Zadnje izmijenjeno od: The Exiled. 10.12.2024. u 19:58.
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Staro 10.12.2024., 22:32   #10300
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Kaže James Prior nedavno, Intel se sad mora izvući iz govana, i postoji recept kako - napisala ga je Lisa Su.
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Staro 10.12.2024., 22:52   #10301
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Mislim da ne bude ništ od toga, tj. da oni nauče iz AMD + Lisa Su lekcija, evo Daniel Nenni u zadnjoj epizodi priča kak se nVidiji posrećilo sa CUDA/AI dijelom priče, a AMD je bil i ostal mala firma koja bez TSMC-a ne bi bila nigdje, makar vidimo kak to Intel odrađuje kad ima napredni TSMC 3nm proces za Arrow Lake. Reko, jebote, pa ovaj je gori i od Gelsingera, čije prezime uporno krivo izgovora, a kao on se pozna sa svim važnim direktorima. U prijašnjim gostovanjima je čak i imal koju pametnu za reći, ali pošto ovakav stručLJak priča takve pizdarije, sve se bojim kaj društvo u Intelu misli kak im ide. Žalosno je da nakon svih Intelovih zajeba, Daniel Nenni i njemu slični pričaju nekaj kaj nema veze s realnošću, ko da je Intel sav jadan sasvim slučajno nabasal na nagaznu minu, pa ih sad treba žaliti i pomoći im na sve moguće načine, jer jedino to je ispravan put i Intel je jedina američka firma vrijedna spomena. Daniel Nenni je komotno ovo gostovanje i izjave mogel poslati mailom.
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Staro 11.12.2024., 07:55   #10302
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Mislim da ne bude ništ od toga, tj. da oni nauče iz AMD + Lisa Su lekcija, evo Daniel Nenni u zadnjoj epizodi priča kak se nVidiji posrećilo sa CUDA/AI dijelom priče, a AMD je bil i ostal mala firma koja bez TSMC-a ne bi bila nigdje, makar vidimo kak to Intel odrađuje kad ima napredni TSMC 3nm proces za Arrow Lake. Reko, jebote, pa ovaj je gori i od Gelsingera, čije prezime uporno krivo izgovora, a kao on se pozna sa svim važnim direktorima. U prijašnjim gostovanjima je čak i imal koju pametnu za reći, ali pošto ovakav stručLJak priča takve pizdarije, sve se bojim kaj društvo u Intelu misli kak im ide. Žalosno je da nakon svih Intelovih zajeba, Daniel Nenni i njemu slični pričaju nekaj kaj nema veze s realnošću, ko da je Intel sav jadan sasvim slučajno nabasal na nagaznu minu, pa ih sad treba žaliti i pomoći im na sve moguće načine, jer jedino to je ispravan put i Intel je jedina američka firma vrijedna spomena. Daniel Nenni je komotno ovo gostovanje i izjave mogel poslati mailom.

To sam baš i ja pomislio. Vidim svi nešto kao "ovo je stručnjaaaaak u PM", a ja si mislim, pa ovo su čiste pizdarije šta lik priča, jesam li ja lud? Ozbiljno sam mislio da ja nešto ne kužim ili propuštam.
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Staro 11.12.2024., 09:21   #10303
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Moguće da tip ima neke gadne pare uložene u Intel, pa je sad lagano panika i zato idu ovakve priče. Makar i u prijašnjim gostovanjima je imal kojekakvih bisera, pa puna usta hvale za direktora Pata koji je "pravi inženjer, on će njih posložiti i postrojiti". Svašta je Daniel napričal, ovisno o tome kak je vjetar zapuhal, ali ova friška epizoda je u rangu bulažnjenja nekog dede koji je davno radil nešto u svijetu mikroprocesora i poluvodiča, pa sad pametuje, a sav zbunjen ne zna da li mu je nešto zagorilo na šporetu.
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Staro 11.12.2024., 13:44   #10304
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haha, tek sada sam dogledao do kraja. Veli on na kraju, u stilu velemudre izjave insajderskog kužera, "I think AMD's graphics chips are actually very good. I think they're better than Intel's." Đizs.
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Staro 11.12.2024., 14:06   #10305
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Da, nadrobil je svašta u tom razgovoru, ali čak i sve njegove gluposti vezano za AMD na stranu, reći da se nVidiji posrećilo na polju CUDA/AI rješenja, stvarno moraš biti stručLJak ko Daniel Nenni. nVidia je skupa s AMD-om kod TSMC-a već nekoliko desetljeća, pa dobro da i nVidiju nije okarakteriziral kao i AMD u kontekstu da je to mala firma, praktički friški startup koji bez TSMC-a nema ništa konkretno. Jadno sve skupa, a za dobru mjeru, veli Daniel u nekoliko navrata Intel 4nm i 3nm proces su ovo-ovo, pa mislim si, frajer ti si još davno pisal članke na temu da Intel 4 i Intel 3 nemaju veze s vezom, jer su zapravo bliže 7nm i 7nm+, a i sve je to ionako samo marketing, pa nema veze kak god se okrene. Jedini zajeb je da neovisno o marketinškom imenu, TSMC i svi njihovi klijenti (uključujući Intel) imaju pristup novim tehnologijama, ali uzalud Intelu najmodernija TSMC rješenja kad su izgubljeni u prostoru i vremenu, dok Daniel Nenni valjda žali za nekim odavnom prošlim zlatnim godinama.
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Staro 18.12.2024., 22:57   #10306
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nisam vidio do sada da AMD ima jos prostora za skalirati, ali nakon ovih par stvari. double down on AMD, vrijeme za poduplati dionice i cekati 2030u zajedno s Nvidiom

samo na temelju HBMa ici ce im market share na serverima do 50% bez problema.
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Staro 06.01.2025., 13:43   #10307
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  • AMD Ryzen 9 9950X3D officially outpaces 7950X3D by 8% and Intel 285K by 20% in gaming
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    AMD confirms that the Ryzen 9 9950X3D will ship with a 5.7 GHz boost clock, identical to the 9950X, and will have a 170W TDP. This processor boasts a total of 144MB cache, significantly more than the non-X3D version, which has 80MB of total cache. The 12-core Ryzen 9 9900X3D features a 5.5 GHz boost clock, 100 MHz lower than the 9900X. It includes 140MB of total cache, compared to 76MB on the non-X3D model, and shares the same 120W TDP.
  • AMD launches Ryzen 9000HX “Fire Range” mobile CPU series, up to 16 Zen5 cores and 140MB cache
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    AMD is officially announcing its new HX-series processors for gaming laptops. Codenamed “Fire Range,” the Ryzen 9000HX series features up to 16 cores based on the Zen 5 architecture. The Ryzen 9 9955HX3D is the flagship model, equipped with 16 cores and a total of 144MB of cache. However, it is expected that this CPU will be reserved for the most high-end gaming laptops. Additionally, AMD is launching the 12-core Ryzen 9 9855HX processor, which features a maximum boost clock of 5.2 GHz and 76MB of cache. It appears that AMD has decided not to introduce additional SKUs for now.
  • AMD Ryzen AI MAX 300 “Strix Halo” APUs bring up to 16 Zen5 cores and 40 RDNA3.5 Compute Units
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    The Ryzen AI MAX series will launch in two variants: the PRO version for business and workstation laptops, and a consumer version. Both variants will feature configurations of up to 16 Zen 5 cores and up to 40 RDNA 3.5 Compute Units. The flagship SKU, Ryzen AI MAX+ (PRO) 395, comes with 16 cores and a boost clock of 5.1 GHz. This APU includes 80 MB of cache and 40 graphics cores. The second-tier model, Ryzen AI MAX (PRO) 390 (without the “+”), features 12 cores, a 5.0 GHz boost clock, 76 MB of cache, and 32 graphics cores. For gaming-focused systems, the Ryzen AI MAX (PRO) 385 may be the most appealing variant. It offers 8 cores and 32 graphics cores. Finally, the Ryzen AI MAX PRO 380 (no consumer variant) is equipped with 6 cores and 16 graphics cores.
  • AMD introduces Ryzen Z2 Series, confirms Valve Steam Deck update
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    The flagship SKU, Ryzen Z2 Extreme, is an 8-core processor based on the Strix Point architecture with Zen 5 cores. It combines three Zen 5 and five Zen 5c cores. This APU includes 16 RDNA 3.5 Compute Units, offering the maximum configuration for this silicon. The lineup also includes the Ryzen Z2 and Ryzen Z2 Go. The Ryzen Z2 Go is a Lenovo exclusive, designed specifically for the Legion Go S. This APU features only 4 Zen 3+ cores and 12 RDNA 2 Compute Units, clearly designed for budget-conscious gamers and systems that don’t require the latest features. The Ryzen Z2 features the Hawk Point APU with 8 Zen 4 cores and 12 RDNA 3 Compute Units. Essentially, this is equivalent to the Ryzen 7 8840U, but it lacks XDNA support, as none of the Ryzen Z-Series APUs include NPU functionality.
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Staro 16.01.2025., 22:20   #10308
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TSMC plans to have 1.6nm chips in 'volume production' by 2026
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The Taiwanese-based biz is looking to secure its share of this sector by ramping production of 2nm chips this year, and pledged volume production of cutting-edge 1.6nm chips for next year. TSMC seems to have a spring back in its step following the global fall in demand for silicon during 2023. Today it reported [PDF] calendar Q4 revenue of $26.88 billion, up 37 percent year-on-year. For Q1 of 2025, TSMC is forecasting a sequential decline in revenue, due to "smartphone seasonality." If accurate, this would see the world's largest chip maker bring in between $25 billion and $25.8 billion, a 5.5 percent drop over today's results, but up 34.7 percent over the same period last year.

However, judging by the capex projections for this financial year, TSMC seems to be in confident mood. It is planning to spend up to $42 billion, compared to $29.8 billion in 2024. Speaking on an analyst conference call to discuss the results, vice chairman and CEO C.C. Wei claimed: "We expect 2025 to be another strong growth year for TSMC, and forecast our full year revenue to increase by close to mid-20s percent in US dollar terms." The past year saw "robust AI-related demand," from AI accelerators including GPUs, ASICs and HBM controllers for training and inference in the datacenter, according to Wei, and he forecast this would double in 2025, as a strong surge in demand continues.

"We expect AI accelerators to be the strongest driver of our HPC platform growth and the largest contributor in terms of our overall incremental revenue growth in the next several years," he said. TSMC's N2 (2nm) process node is "well on track" for volume production in the second half of 2025, as scheduled, Wei said. This is expected to offer a 10 to 15 percent speed improvement at the same power versus N3E technology, or a 20 to 30 percent power improvement at the same speed, and an increase of more than 15 percent in density.

He also mentioned TSMC's A16 technology, which is scheduled to produce the first 1.6nm chips by 2026. This will be available with Super Power Rail, TSMC's version of the backside power delivery approach detailed by Intel, and the node is to feature a further 8 to 10 percent speed improvement at the same power compared with N2, and an additional 7 to 10 chip density gain. "Volume production is scheduled for second half 2026," Wei claimed. On the company's fabrication plant projects, the first fab in Arizona entered high-volume production last quarter, using N4 (4nm) process technology with a yield comparable to TSMC's fabs in Taiwan.

Plans for a second and third fab in Arizona are also on track, with those facilities intended to operate more advanced technologies such as N3, N2, and A16 (3nm, 2nm and 1.6nm) "based on our customers' needs," Wei said. In Japan, a "specialty technology" fab in Kumamoto started volume production at the end of 2024, while construction of a second is scheduled to begin this year. And plans for TSMC's first fab in Europe continue, with commitment from the European Commission and German federal, state and city government for the site in Dresden intended to produce automotive and industrial chips. For the fourth quarter, 5nm chips still made up the bulk of TSMC's revenue (43 percent), but 3nm caught up fast at 26 percent, while 7nm is now down slightly to 14 percent. In terms of platforms, products for the high performance compute (HPC) sector dominated at 53 percent of revenue, with smartphone chips making up 35 percent.
Izvor: The Register
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AMD to build Zen 6 CCD on TSMC 3nm process, next-gen cIOD and sIOD on 4nm
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AMD is rumored to be building its next-generation CCD (core complex die) that implements the "Zen 6" microarchitecture, on the 3nm TSMC N3E foundry node. Apparently, AMD will also refresh the I/O dies for its next generation process, building them on the 4nm foundry node, likely the TSMC N4C. The TSMC N3E node offers a 20% speed improvement, over 30% power savings, and approximately 60% logic density increase over TSMC N5, whereas the TSMC N4P node that the company uses for its current "Zen 5" chiplets only clock minor increases in logic density and power over N5. The N3E node relies on EUV double-patterning to achieve its logic density increases.

Perhaps the most interesting piece of news is the new-generation I/O dies. AMD is building these on the 4nm node, which is a significant step up from the 6nm node its current I/O dies are built on. On the client side of things, 4nm will enable AMD to give the new cIOD an updated iGPU, probably based on a newer graphics architecture, such as RDNA 3.5. It will also give AMD the opportunity to give its desktop processors an NPU. It will also give the company a chance to update its key I/O components, such as the DDR5 memory controllers, to support higher memory speeds unlocked by CUDIMMs. We don't predict any updates on the PCIe front, since AMD is expected to carry on with Socket AM5, which determines that the cIOD puts out 28 PCIe Gen 5 lanes. At best, the USB interface put out from the processor could be updated to USB4 through an on-die host controller. Over on the server side, the new-generation sIOD will bring much needed increases to the DDR5 memory speeds enabled by clock drivers.

The rumor mill also churns out something on graphics. Depending on how the Radeon RX 9000 series and RDNA 4 fare in the market, AMD could revisit the enthusiast segment with its next generation UDNA architecture that the company will make common to both graphics and compute. The company's next-generation discrete GPUs will be built around the TSMC N3E foundry node.
Izvor: TechPowerUp
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Zadnje izmijenjeno od: The Exiled. 17.01.2025. u 09:18.
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Staro 05.02.2025., 09:53   #10309
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AMD reports fourth quarter and full year 2024 financial results
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AMD today announced financial results for the fourth quarter and full year of 2024. Fourth quarter revenue was a record $7.7 billion, gross margin was 51%, operating income was $871 million, net income was $482 million and diluted earnings per share was $0.29. On a non-GAAP basis, gross margin was 54%, operating income was a record $2.0 billion, net income was a record $1.8 billion and diluted earnings per share was $1.09. For the full year 2024, AMD reported record revenue of $25.8 billion, gross margin of 49%, operating income of $1.9 billion, net income of $1.6 billion, and diluted earnings per share of $1.00. On a non-GAAP basis, gross margin was a record 53%, operating income was $6.1 billion, net income was $5.4 billion and diluted earnings per share was $3.31. During a recent Q4 2024 earnings call, AMD CEO Dr. Lisa Su confirmed that the launch will happen in early March. She specifically stated that these cards will go on sale, which presumably means a full product launch rather than preorders. She also mentioned that the company will target the “volume portion of the enthusiast market.”

No one could have predicted how fast Nvidia would have expanded in the wake of GenAI, and no one would have predicted how far – and how fast – Intel has fallen. But what is truly a thing to behold – and what is far more important than being right, after all – is how far AMD has come in a decade and to ponder what AMD might do in the next decade as computing inevitably evolves in the datacenter and in our handheld devices. It is with that broad expanse in mind that we contemplate the financial results that AMD just turned in for 2024. The company is humming along on all fronts, but its numbers also show that it is still incredibly expensive to create the high end PC and server devices that the company proudly crafts and peddles, and therefore it is always a challenge to rake in the profits when it believes in open source software and cannot make a moat like other companies in the history of IT have been able to do – like IBM and Nvidia, to name two who are still doing it largely because of the proprietary and closed source nature of their software stacks.
Izvor: The Next Platform
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Staro 15.02.2025., 14:27   #10310
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AMD Zen 6 powers "Medusa Point" mobile and "Olympic Ridge" desktop processors
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AMD is readying two important client segment processors powered by the next-generation "Zen 6" microarchitecture, according to a sensational new report by Moore's Law is Dead. These are the "Medusa Point" mobile processor, and the "Olympic Ridge" desktop. The former is a BGA roughly the size and Z-Height of the current "Strix Point," but the latter is being designed for the existing Socket AM5, making it the third (and probably final) microarchitecture to do so. If you recall, Socket AM4 served three generations of Zen, not counting the refreshed "Zen+." At the heart of the effort is a new CPU complex die (CCD) that AMD plans to use across its client and server lineup.

The "Zen 6" performance CCD is being designed for a 3nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.

Going all the way back to the Ryzen 3000 series "Matisse," the two CCDs on the client desktop processor have had Infinity Fabric links to the I/O die, but no direct high-bandwidth interconnects between the two CCDs. For threads to migrate between cores of the two CCDs, they would have to make a round-trip through the main memory. AMD is looking to solve this with the introduction of a new low-latency bridge connection between the two CCDs. If the goal is to enable threads to seamlessly migrate among cores of the two CCDs, cutting out round-trips to the main memory, then the purpose of this bridge interconnect is to establish cache coherency between the two CCDs. This would vastly lower intercore latency.

Here's where things get very interesting. Apparently, the "Medusa Point" mobile processor is chiplet-based, and will use a single 12-core "Zen 6" chiplet, with a large mobile client I/O die built on an older node, likely the N4P. This mobile cIOD will contain an updated iGPU that's powered by the newer RDNA 4 graphics architecture. It will also contain the chip's memory controllers, and an updated NPU. We hope AMD works to increase the number of PCIe lanes put out by this I/O die, or at least update it to PCIe Gen 5. Pictures show small rectangular structures on the mobile client I/O die causing some speculation that it is some kind of low power island CCX with "Zen 6c" cores, although MLID lays this to rest by saying that these are workgroup processors (WGPs) of the iGPU. There are eight of these and a large slab of L2 cache, which seems to confirm that the iGPU is based on the RDNA 4 graphics architecture, and has 16 compute units (CU).

Since AMD is using the same CCD for "Medusa Point" as the "Olympic Ridge" desktop processor, you could expect variants of "Medusa Point" with 3D V-Cache. The 3D V-Cache technology is expected to be implemented on "Zen 6" much in the same way it is on "Zen 5," with an upside-down stacking—3D V-Cache die (L3D) below, with CCD on top.

Given the increase in CPU core counts, especially with "Olympic Ridge" getting up to 24 cores with two CCDs, and the inter-CCD bridge interconnect for cache coherency, AMD is going to need a new client I/O die for desktop. We've already discussed this in older articles. The new cIOD is expected to be built on the Samsung 4LPP (4 nm EUV) foundry node, which offers improvements over the TSMC N6 DUV node the current cIOD is being built on. A key area of focus for AMD will be the memory controllers, which will be updated to support higher DDR5 memory speeds using technologies such as CKD. You can currently run a "Granite Ridge" processor with memory speeds of up to DDR5-8000 but using a 1:2 clock divider is engaged between FCLK and MCLK, with 1:1 speeds being limited to around DDR5-6400. The new memory controllers will look to increase speeds with 1:1, and unlock speeds beyond 10000 MT/s with 1:2.

Then there's the matter of AI acceleration, and the new cIOD will present AMD with the opportunity to implement at least a 50 TOPS-class XDNA 2 NPU. Intel received flack for giving its "Arrow Lake" processors a 16 TOPS-class NPU that doesn't meet Copilot+ requirements, and the company is probably working to fix this in "Panther Lake," and so if AMD decides to implement an NPU on the cIOD for "Olympic Ridge," we predict it will be at least 50 TOPS-class.
Izvor: TechPowerUp
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Staro 08.03.2025., 18:25   #10311
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AMD’s next-gen Ryzen Zen 6 “Medusa Ridge” CPUs to come in 12, 24 & 32-core flavors, up to 128MB L3 cache
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It looks like we finally have some new information on the core and cache counts of the next-gen Zen 6-based Ryzen offerings. The company has already announced the continuation of its high-performance journey with new Zen 6 and Zen 6C cores, which will be heading out to server, laptop, and desktop platforms. These CPUs are also expected to land on the same AM5 socket, which will be great for those who have invested in the latest motherboards. Previously, it was reported that AMD's Zen 6 CPUs would come in CCD configurations ranging from 8, 16 and up to 32 cores. This alone would mark a doubling of the max core count versus existing Zen lineups.

It looks like the AMD Ryzen "Zen 6" CPUs, which are codenamed under the "Medusa Ridge" series, will come in 12, 24 and 32 core parts. The 12 and 24 core variants will feature a 96MB cache, while the maximum cache will be 128 MB, the 12-core Zen 6 CCD will feature a 48MB L3 cache while the 32-core variant will pack a 128MB L3 cache. The 32-core variant will come with Zen 6C cores instead of the vanilla Zen 6 cores. It is also said that desktop non-X3D CPUs will feature two 48MB L3 cache clusters or 48MB per CCD, which will round up to 96MB.

The standard AMD Zen 6 CCDs will offer a 50% increase in cache count over the Zen 5 cores, while the Zen 6C CCDs will offer double the cache count uplift versus Zen 5. Also, these are all non-X3D parts, so we can expect even higher caches with those models. AMD has already leveraged its 2nd Generation 3D V-Cache in Ryzen 9000 "Zen 5" CPUs so next-gen Ryzen can further boost the cache counts and even bring forth dual-X3D variants if there's a need for it though the company says that it all comes down to economics and the reason they haven't done dual X3D caches is not due to technical limitations.
Izvor: Interneti
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Staro 16.03.2025., 00:51   #10312
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Ako Zen 6 bude 12 Core CCD i bude kompatibilan sa AM5 platformom to će zaista biti spektakularan način za završiti AM5 platformu. Ja sam bio kupio 7600x "za prvu ruku" kad je tada tek izašao i kada bi za ~ god. dana u isti taj socket mogao ubaciti 12 Core + 3d cash zvijer bio mi miran zaista jako dugo vremena. Vjerovatno cijelu PS6 generaciju igrica
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Staro 28.03.2025., 11:36   #10313
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Izgleda da bude od svega pomalo uz naglasak na mnoštvo APU modela, dok je Zen 6 dodatno potvrđen za AM5 platformu.
AMD Zen 6 specs leak: 6GHz+ TSMC N2X, 26 Cores, 2-Hi X3D, RDNA 4 (Medusa, Olympic, Gator, Bumblebee)
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Staro 28.03.2025., 17:06   #10314
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Valjda će doći modeli sa 105w tdp. Čisto da pokrije sredinu koju je falilo u Zen5 sa 65 i 120w
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Staro 28.03.2025., 17:51   #10315
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Nadolazeći AMD socketi, ploče i procesori

A i taj TDP… već sad entry level modeli mogu cuclati od 65W do 120-140W ovisi kako podesiš u BIOSu.
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Staro 28.03.2025., 19:33   #10316
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jedno OT pitanje, nisam baš pratio AMD ali kako stvari stoje, počet ću

zanima me sljedeće, zašto je recimo 9800x3d ryzen 7, a 9950x3d je ryzen 9

to ovisi samo o broju corova ili?

meni bi bilo logično da je ryzen 7 7800x3d, ryzen 9 9800x3d, ali nije tako
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Staro 28.03.2025., 19:38   #10317
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Da, broj jezgri je zajednički nazivnik, ali možda i to s vremenom izmjene kad se s generacijama postepeno povećava broj jezgri.
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Staro 28.03.2025., 20:25   #10318
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Ali je malo nelogično što su i 12c/24t i 16c/32t ryzeni 9, prvi bi trebali biti ryzen 9, a drugi ryzen 11
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Staro 28.03.2025., 23:54   #10319
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jedno OT pitanje, nisam baš pratio AMD ali kako stvari stoje, počet ću

zanima me sljedeće, zašto je recimo 9800x3d ryzen 7, a 9950x3d je ryzen 9

to ovisi samo o broju corova ili?

meni bi bilo logično da je ryzen 7 7800x3d, ryzen 9 9800x3d, ali nije tako
Ako ćeš se rješavat tog svojeg i7 13th, javljam se sa štovanjem. (Vjerojatno nije defektan.)
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Staro 28.03.2025., 23:59   #10320
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ma neću još, radi ko urica sve, ali kroz par godina
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