[Manuel Calavera]

AMD’s Mark Papermaster has just confirmed that the companies engineers are currently in the design phase of the Zen 5 CPU architecture.
Details were scarce on what we’ll see on the Zen 5 design, but during the EPYC Horizon executive event, AMD confirmed their leapfrog approach for chip design was paying off, and that their long term roadmap was looking extremely healthy.


Earlier this year, an engineer at AMD accidentally confirmed Zen 5’s existence by listing it as an accomplishment on LinkedIn.


From what little we know about Zen 5, it will be produced on TSMC’s 5nm process. Aside from that, we can gather it will support next-generation memory, as we know that Zen 3 will be the final series of processors supporting the older DDr4 standards, and also mark the end of the legacy/backwards compatibility promise AMD made back in 2017 for both the server and mainstream line up (AM4).

Oh, and speaking of the EPYC Horizon event, AMD wheeled out TSMC’s Godfrey Cheng (who serves as TSMC’s head of Global Marketing head) in an effort to assure customers that TSMC could handle the capacity demands of AMD.


“In raw aggregate capacity, we’re actually three times the capacity of our next nearest foundry competitor. This means that we have approximately 12,000,000 12-inch equivalent wafers in terms of raw capacity.”
He then went on to state that their “N7 node has actually been very successful.” and that they’d been able to ramp up production quickly, the fastest in any node on TSMC’s own history.