Citiraj:
Autor guerra
Ili im je jednostavno arhitektura neefikasna kao i do sada pa potrosnja nakon odredene granice skace u nebo.
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Brkaš kruške i jabuke, ovo što si napisao da potrošnja nakon odredjene granice ode u nebo nema(ili ima jako malo) veze sa arch vec puno više ovisi o proizvodnom procesu gdje nakon neke granice od xyz mhz moraš ni blizu proporcionalno dizati voltažu sa svaki dodatni mhz takta, tj. krivulja više nije linearna vec pocne poprimati oblik parabole.
Primjer za zen1 od stilta:
Citiraj:
The overclocking headroom for the higher-end Ryzen models is rather slim. This was expected due to the relatively high stock frequencies, high-density orientation of the design and the low power targeted manufacturing process used for the Zeppelin die (Samsung 14nm LPP).
As indicated by the Vmin-Fmax curve, Zeppelin's voltage scaling is perfectly linear until 3.3GHz (25mV per 100MHz). The first deviation ("Critical 1") from this linear behavior can be seen at 3.3GHz. The second and the final deviation ("Critical 2") can be seen at 3.5GHz. Beyond this point the voltage scaling is neither linear or recovers even temporarily, and the CPU is requiring higher voltage in increasingly larger steps to scale further.
The ideal frequency range for the process or the design (as a whole) appears to be 2.1 - 3.3GHz (25mV per 100MHz). Above this region (>= 3.3GHz) the voltage scaling gradually deteriorates to 40 - 100mV+ per 100MHz.
This means that at ~3.8GHz pushing further usually becomes extremely costly (power / thermal wise).
In comparison, the "critical" points for the two previous AMD desktop designs were at:
- Orochi Rev. C aka Vishera, 32nm SHP SOI - (1 = 4.4GHz, 2 = 4.7GHz)
- Kaveri / Godavari, 28nm "SHP" HPP Planar - (1 = 4.3GHz, 2 = 4.5GHz)
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