[The Exiled]

AMD EPYC Genoa: 128 core, 16 CCDs, 12-channel DDR5-5200

We had received information pertaining to Genoa and had a hard time believing it initially, as 128 cores is a large jump over the more-reserved rumor of 96 cores going around. However, today’s Milan-X leak, which confirmed our “ZenX” leak from two and half years ago, certainly clarified things. In Jim’s EPYC Update video from back then, our information was basically only that ZenX was a thing and that it was being kept very close to the chest. Speculation back and forth behind the scenes was that it could be chip stacking. It could have been CPU+GPU+RAM, 3D stacking, an active interposer, we weren’t sure. Milan-X with “X3D” Packaging (as mentioned during AMD’s Financial Analyst Day on March 5th, 2020) could be a key technology forerunner for Genoa.

Looking through the rest of our leak, we get die sizes of ~69 mm² on TSMC 5nm for the Zen4 chiplets and ~263 mm² on TSMC 6nm for the IOD. The size reductions were a given due to the die shrink, but the most notable is the massive 37% reduction in IO die size, enabled by the switch from GlobalFoundries to TSMC’s 6nm node. With AMD’s recently revised seventh amendment to their Wafer Supply Agreement with GlobalFoundries, which notably drops all exclusivity agreements (outside the minimum order requirements for 2022, 2023, and 2024 of course), this certainly lines up with AMD selecting TSMC for manufacturing of the next-gen IODs for EPYC and Ryzen. 12/14nm nodes can still fill previous-gen, embedded, or specialty (Chromebook) CPU orders and serve as cheap competitors to Intel’s low-end CPUs, without AMD having to waste modern-node wafers on small dual or quad core CPUs for slim margins, just to flesh out a lineup.

AMD EPYC Genoa will be competing with Intel’s Sapphire Rapids 4th Generation Xeon server CPU, which boasts 56 cores and 8-Channel DDR5-4800. Those mere 56 cores require four 15-core Golden Cove dies at 372mm² each, fabbed on 10nm++ and glued together with Intel’s EMIB (Embedded Multi-Die Interconnect Bridge) technology, and has 112 MB of L3 cache. While these specs line up fairly well with AMD’s current Milan 7003-series EPYC CPUs, those CPUs have already launched, whereas Sapphire Rapids isn’t due until 2022, where it will be met head-on with Genoa, which will likely be cheaper to manufacture and clock higher at better TDPs; a veritable hat trick in the semiconductor industry for sure.

Izvor: AdoredTV