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Autor Ghostrid3r
Sto su to L3 cache i TLB?
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OK, primjetio sam da imaš puno pitanja i puno otvorenih tema!
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L3 cache = treće razredni "keš" dosta veći i sporiji od L2 cachea koji je isto dosta sporiji i veći od L1 cachea.
Translation Lookaside Buffer (
TLB) is a
CPU cache that is used by
memory management hardware to improve the speed of
virtual address translation. All current desktop and server processors (such as
x86) use a TLB. A TLB has a fixed number of slots containing
page table entries, which map virtual addresses onto
physical addresses. It is typically a
content-addressable memory (CAM), in which the search key is the virtual address and the search result is a physical address. If the requested address is present in the TLB, the CAM search yields a match very quickly, after which the physical address can be used to access memory. If the requested address is not in the TLB, the translation proceeds using the
page table, which is slower to access. Furthermore, the translation takes significantly longer if the translation tables are swapped out into secondary storage, which a few systems allow.
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