PC Ekspert Forum - View Single Post - Nadolazeći AMD socketi, ploče i procesori

The Exiled · 03.09.2025., 19:05

Citiraj:

AMD Zen 6 processors to use TSMC 2nm node for CCDs, 3nm for IOD

Citiraj:

AMD will transition its next-generation "Zen 6" desktop Ryzen and server EPYC processors to a split-node strategy, placing CPU core complex die (CCD) on TSMC N2P 2nm node variant and building the I/O die (IOD) on the N3P 3nm node. At TSMC, volume ramp for the 2nm node is around the third quarter of 2026, opening the door for limited shipments as early as late Q3 or broader availability in Q4 2026. Under the split approach, the compute chiplet will house the Zen 6 cores and a substantially larger shared L3 pool, while the IOD will continue to host memory controllers, PCIe lanes, USB, and the integrated GPU.

With its next-generation I/O Dies, AMD plans to jump from TSMC’s N6 node to N3P. This means that AMD’s next-generation CPUs will leverage several node transitions to achieve a significantly larger-than-normal generational performance leap. Instead of benefitting from a single node shrink, AMD is jumping several generations ahead. For its CPU CCDs, AMD is jumping from TSMC N4 to N2P, skipping N3. With its I/O Dies, AMD is jumping from N6 to N3, skipping N5 and N4. Furthermore, AMD plans to use TSMC’s performance-optimised P-series nodes. Instead of N2 and N3, AMD is using N2P and N3P.

Earlier rumors suggest that each CCD could contain 12 Zen 6 cores with support for SMT, and a shared L3 cache that may increase to roughly 48 MB per CCD compared with prior generations. Typical consumer configurations would pair up to two CCDs with a single IOD, creating chips with up to 24 cores and 48 threads. Performance expectations center on achieving double-digit IPC gains, higher sustained clock speeds, and improved power efficiency, thanks to the advanced process nodes. The choice of N3P for IOD helps AMD cut some costs for non-core logic, while the N2P compute die aims to extract greater generational gains. However, as with any new TSMC node, it will carry a premium over the N3P, so using it only for the compute side is the most viable choice. Platform compatibility remains for one more generation, with Zen 6 expected to support the existing AM5 socket.

Izvor: TechPowerUp i OC3D

EDIT:

Citiraj:

AMD D2D interconnect in "Zen 6" gets Sea-of-Wires upgrade

Citiraj:

According to the High Yield YouTube channel, AMD is reportedly moving away from SERDES-based die-to-die links and toward a wide, parallel "sea-of-wires" routed through fan-out and RDL packaging, and the first hints of that change showed up in Strix Halo APU photos. The samples reveal a rectangular pad field where you would expect a fan-out, and the large SERDES block that used to sit at CCD edges is noticeably absent. That pattern, along with packaging choices consistent with TSMC's InFO-oS, suggests AMD is trying out dense parallel traces so fabric lanes can cross the package without being channeled into a few separate high-speed serial links. Usual serializing and deserializing data at every package boundary uses power and adds latency, thanks to clock recovery, equalization, and encoding and decoding overhead.

By moving to many short parallel wires, AMD can eliminate repeated PHY work and reduce round-trip delays, while allowing raw bandwidth to scale by adding physical lanes. The approach also frees the area that was once consumed by large SERDES blocks, which could let CCDs, memory controllers, and accelerators sit closer together with lower communication cost. There are real tradeoffs to solve, though. Packing lots of parallel traces under a die raises signal integrity, thermal, routing, and manufacturing challenges, so multi-layer RDL design and close co-engineering between die and package teams will be essential. If AMD can address those issues and carry the approach into Zen 6, we could see real per-watt and latency improvements for CPU workloads, including a faster memory IMC, thanks to lowered latency from the I/O die.

Izvor: TechPowerUp