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The Exiled · 01.09.2025., 08:55

Nažalost nofci od države su samo kap u moru koliko Intelu zapravo treba da svoje proizvodne pogone dovede na TSMC nivo, a sad su im za ovih 5.7 milijardi koje su već dobili stavili dodatne klauzule koje im zabranjuju korištenje tih novaca za isplaćivanje dividendi i(li) otkup dionica, dok financijski direktor ponosno priča kak će sredstva biti od velike pomoći za sveukupnu bilancu. Tak da kak god se okrene, njima je svaki sljedeći kvartal uvijek ključan u tom začaranom krugu. Koliko im ova potencijalna SDC implementacija u nastavku ima smisla, ostaje za vidjeti, posebice kad su za 2028. već najavili da odustaju od hibridnog pristupa, odnosno nadolazeće arhitekture se više neće oslanjat na male (E) i velike (P) jezgre, dok istovremeno planiraju ponovo vratiti HT/SMT, jer su i tu skužili zajeb svojih bajnih odluka tokom godina.

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Intel patents software-defined super cores to maximize single-core performance

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To maximize its CPU performance, Intel has filed a patent that describes a new way to boost single-thread performance by letting several smaller cores work together as if they were one larger core. Instead of chasing higher clock speeds or building ever-bigger cores, the idea is to dynamically fuse two or more physical cores so they cooperatively execute a single thread, while appearing to the operating system as a single logical core. The patent refers to this approach as Software Defined Super Cores, or SDC. The technique would split an instruction stream into chunks and hand those chunks to the fused cooperating cores. Those cores would coordinate closely, utilizing special buffers and fast communication paths to ensure correct memory ordering and data transfers. In heavier single-threaded cases, the processor can enter a fused mode, forming a "super core" that aggregates instructions per cycle without requiring higher voltage or frequency, which can improve performance per watt.

Keeping instructions in strict program order across multiple physical cores requires very low-latency inter-core messaging and careful synchronization, as well as scheduling the fused cores so they actually benefit real applications, which is a challenging software problem. Presumably, compiler magic would be needed to extract maximum bandwidth from this approach, which is something that made Intel's Itanium fail. If the approach can be made practical, it would give chip designers another way to scale single-thread performance beyond process shrinks and larger core designs. Whether we ever see an SDC design in shipping silicon will depend on the results of prototypes and how well operating systems and compilers can leverage the mode. Intel is constantly experimenting with new core architectures, but not everything makes it to volume production due to low feasibility.

Izvor: TechPowerUp