Da, tak ispada, a Intel si je nažalost fino smjestil, dok ovi u AMD-u više ne znaju za mjeru, pa polako, ali sigurno sve moguće serverske ubojice fazana s vremenom dovode na desktop i HEDT.
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Intel was the first of the major CPU makers to add HBM stacked DRAM memory to a CPU package, with the “Sapphire Rapids” Max Series Xeon SP processors. But with the “Granite Rapids” Xeon 6, Intel abandoned the use of HBM memory in favor of what it would hope would be more main stream MCR DDR5 main memory, which has multiplexed ranks to boost bandwidth by nearly 2X over regular DDR5 memory. Importantly, the EPYC 9V64H has 128 GB of HBM3 memory that runs at a peak 5.2 GHz clock speed and that provides an aggregate of 5.3 TB/sec of peak memory bandwidth. A regular Genoa SP5 CPU socket using 4.8 GHz DDR5 memory delivers 460.8 GB/sec of bandwidth across a dozen DDR5 memory channels, by comparison. So this is a factor of 11.3X higher memory bandwidth across the same 96 cores of Genoa compute. By the way, the Xeon SP Max Series CPUs launched in November 2022 had four stacks of HBM2E memory with a total of 64 GB of capacity and in excess of 1 TB/sec of aggregate bandwidth out of that memory. AMD is delivering 71 percent more cores, 2X the memory capacity, and somewhere around 5X the memory bandwidth of the Intel CPU with HBM.
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Izvor: The Next Platform
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Uopće ne bi bilo čudno da s nadolazećim generacijama iskombiniraju 3D cache
+ HBM pod istim IHS-om, pa sve skupa zapakiraju za obične smrtnike.
