AVX10.2 će dodati punokrvnu podršku za manje šparne (E) jezgre, a to stiže tek nakon Arrow Lake i Granit Rapids modela s velikom šansom da kompletni Arrow Lake koristi TSMC 3nm koji ionako potvrđeno radi sve chiplete uz mogućnost CPU-a.
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Intel says that version 1 of the AVX10 vector ISA (AVX10.1) will first be implemented on Intel Xeon “Granite Rapids” processors that, according to some media reports, are expected to launch by 2024 or 2025, so it will likely take a long while before AVX10.2 is implemented on processors with E-cores. In Intel's first phase of AVX10 (AVX10.1), this will be introduced for early software enablement and will support the subset of Intel's AVX-512 instruction sets, with Granite Rapids (6th Gen Xeon) performance (P) cores being the first cores to be forward compatible with AVX10. It is worth noting that AVX10.1 will not enable 256-bit embedded routing. As such, AVX10.1 will serve as an introduction to AVX10 to enable forward compatibility and implementation of the new versioning enumeration scheme.
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Izvor: Intel i AnandTech
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Zadnje izmijenjeno od: The Exiled. 17.08.2023. u 20:11.
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