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The Exiled · 19.03.2022., 16:43

Nadolazeći Intel Sapphire Rapids Xeon HBM modeli mogu funkcionirati bez dediciranog sistemskog RAM-a.

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Intel states that SPR-HBM can be used with standard DDR5, offering an additional tier in memory caching. The HBM can be addressed directly or left as an automatic cache we understand, which would be very similar to how Intel's Xeon Phi processors could access their high bandwidth memory. Alternatively, SPR-HBM can work without any DDR5 at all. This reduces the physical footprint of the processor, allowing for a denser design in compute-dense servers that do not rely much on memory capacity (these customers were already asking for quad-channel design optimizations anyway).

The amount of memory was not disclosed, nor the bandwidth or the technology. At the very least, we expect the equivalent of up to 8-Hi stacks of HBM2e, up to 16GB each, with 1-4 stacks onboard leading to 64 GB of HBM. At a theoretical top speed of 460 GB/s per stack, this would mean 1840 GB/s of bandwidth, although we can imagine something more akin to 1 TB/s for yield and power which would still give a sizeable uplift. Depending on demand, Intel may fill out different versions of the memory into different processor options. One of the key elements to consider here is that on-package memory will have an associated power cost within the package. So for every watt that the HBM requires inside the package, that is one less watt for computational performance on the CPU cores.

Izvor: AnandTech

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Autor kiki85

i sto ih ogranicava da je cache memorija tako mala 512KB 4mb 96mb

Dosad je razlog bila povećana cijena samog CPU-a uz veće/više latencije i manjak (on-die) prostora za ostale funkcionalnosti/komponente/logiku.

Zadnjih godina priča se okreće prema MCM i opećnito chiplet rješenjima uz stacked, odnosno 3D cache implementacije - nove CPU i GPU arhitekture dolaze sa sve većim količinama cachea.

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Infinity Cache at a high level, this is a sizable on-chip cache that according to AMD functions a lot like an L3 cache on a CPU. Just how similar remains to be seen, but conceptually, it can be thought of as a local cache that buffers against reads and writes to the main memory, and provides a backstop for large operations that’s a lot faster than having to go out to VRAM. About 20% the "Navi 21" silicon die area now holds what AMD calls the "Infinite Cache," which is really just a new L3 cache that is 128 MB in size and talks to the GPU's four shader engines at 1024 bits per pin, per cycle. This cache has an impressive bandwidth of 2 TB/s and can be used as a victim cache by the 4 MB L2 caches of the four shader engines.

Izvor: TechPowerUp