PC Ekspert Forum - View Single Post - Nadolazeći AMD socketi, ploče i procesori

The Exiled · 28.05.2021., 19:02

Mogu kaj god ih volja, tim više, jer njihov hibridni pristup se i dalje temelji na Zen arhitekturi. Nisu kao Intel morali posezati za nečim skroz drukčijim, pa smanjivati cache, micati instrukcije i tome slične ekskurzije. Naposljetku kombinacija Zen 5 + Zen 4 jezgri neće biti puno drugačija od ovoga kaj imamo danas, samo kaj će unutar istog chipleta ili kombinacije nekolicine chipleta, složiti dvije Zen generacije, dok OS i aplikacije neće raditi ni vidjeti razliku između jednih ili drugih. Taj dio priče su započeli s prvom Threadripper generacijom i usavršili s Renoir i Lucienne implementacijom. U slučaju srezanih efikasnih "manjih" Zen 4 jezgri to može značiti jednostavno ograničavanje PBO2, odnosno Turbo funkcionalnosti, dok sve ostalo ostaje isto i na mjestu, a takve jezgre na kakvih 3.5GHz do 4.0GHz će itekako i dalje biti i više nego sposobne. Velim, AMD je teži dio posla već odradil, ovo kaj slijedi u godinama koje dolaze su samo finese.

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For Cezanne and Lucienne, AMD is implementing several CPPC2 features first exhibited on desktop silicon to try and get the most out of the silicon design. ‘Preferred Core’ is a term used mostly on the desktop space to indicate which CPU core in the design can turbo to the highest frequency at the best power, and through a series of operating system hooks, the system will selectively run all single-threaded workloads on that core assuming no other workload is present. Previously, threads could bounce around to enable a more equal thermal distribution – AMD will now selectively keep the workload on the single core until thermal limits kick in, enabling peak performance and no extra delays from thread switching.

Another part of CPPC2 is frequency selection, which reduces the time for the transition from low-frequency to high-frequency from 30 milliseconds down to under 2 milliseconds. The consequences of this enables workloads that occur for shorter than 30 milliseconds can take advantage of a momentarily higher frequency and get completed quicker – it also enables the system to be more responsive to the user, not only in idle-to-immediate environments, but also in situations where power is being distributed across the SoC and those ratios are adjusting for the best performance.

The third part of CPPC2 is the migration away from discrete legacy power states within the operating system. With an OS that has a suitable driver (modern Windows 10 and Linux), frequency control of the processor is returned back from the OS to the processor, allowing for finer grained transitions of when performance or power saving is needed. This means that rather than deal with the several power states we used to, the processor has the full continuous spectrum of frequencies and voltages to enable, and will analyze the workflow to decide how that power is distributed (the operating system can give hints to the processor to aid in those algorithms).

Izvor: AnandTech

AMD već sad ima sve potrebno za ovo kaj se potencijalno sprema sa Zen 5 + Zen 4 kombinacijom, jer ni današnji im modeli nisu ništa manje hibridni od ovih nadolazećih, samo su (još uvijek) temeljeni na istoj arhitekturi za sve jezgre.

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ARM big.LITTLE

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The big news is the Cortex A7 is 100% ISA compatible with the Cortex A15, this includes the new virtualization instructions, integer divide support and 40-bit memory addressing. Any code running on an A15 can run on a Cortex A7, just slower. This is a very important feature as it enables SoC vendors to build chips with both Cortex A7 and Cortex A15 cores, switching between them depending on workload requirements. ARM calls this a big.LITTLE configuration. Since the A7 and A15 are equally capable of executing the same ARM instruction set, any applications running on one core can just as easily be migrated to run on the other. In this particular configuration, the OS only believes there are two cores in the machine. ARM’s own power management firmware determines which core cluster to activate depending on performance states requested by the OS. If the OS wants a high performance state, ARM returns the A15 cores at a high p-state. If it wants a low performance state, the chip will put the A15s to sleep and schedule everything on the A7s. If everything works the way ARM has described it, a big.LITTLE configuration should be perfectly transparent to the OS.

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Intel Alder Lake

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Alder Lake processors are based on a new hybrid architecture that utilizes two core types: high-performance and high-efficiency. According to Intel, Alder Lake is a "performance hybrid" in their portfolio as it focuses on performance. Intel also claims that Alder Lake will have their best performance per watt. Next generation hardware scheduler adding support for these advanced scheduling capabilities will require Microsoft to add support for them to x86-64 Windows. For products that come with mixed cores, the nominal instruction set is only SSE without AVX. In other words, there is no ISA incompatibility and there is currently no asymmetric ISA support.