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McG
Datum registracije: Feb 2014
Lokacija: Varaždin
Postovi: 8,194
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TSMC Q1 2021 process node revenue: More 7nm, no more 20nm
Citiraj:
7nm accounts for 35% of all revenue, with 5nm now at 14%. This might seem odd, however TSMC has very few customers with 5nm designs, but plenty for 7nm, suggesting that TSMC is able to have customers bid against each other (along with increasing wafer output). For the last few quarters, reports about TSMC’s 7nm lead time for products, from order to production to shipment, have been extending due to the increased demand. Note that TSMC’s most advanced packaging technologies, such as CoWoS, are typically used in conjunction with 7nm or 16nm silicon, so those revenues are likely in those respective segments as well.
Recently TSMC has stated that it plans to spend $100B over the next three years to increase capacity leading-edge capacity, which includes the $25B-$28B it had already planned for 2021, with $12B of that going onto a factory in Arizona. Apparently an eye-watering $25 billion to $28 billion in capital expenditure just wasn’t enough to satiate global demand, so the Hsinchu-based company raised it to $30 billion. Revenue from 16nm is decreasing, now going below 15% for a couple of quarters, and showcasing that TSMC is making as much money from 16nm as it is from 5nm and 90nm+ older process nodes. TSMC’s most-advanced technologies continued to account for nearly half of revenue in the March quarter, with 5-nanometer and 7-nanometer processes contributing 14% and 35% of sales, respectively. By business segment, its smartphone business amounted for about 45% of revenue, while HPC increased to more than a third, reflecting sustained demand for devices and internet servers even as economies start to emerge from the pandemic.
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Izvor: AnandTech, Bloomberg ( 1 - 2) i DigiTimes
EDIT:
Citiraj:
TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022
Citiraj:
As far as capacity is concerned, TSMC is unchallenged and is not going to be for years to come. As for fabrication technologies, TSMC has recently reiterated that it's confident that its N2, N3, and N4 processes will be available on time and will be more advanced than competing nodes. About 80% of TSMC's $30 billion capital budget this year will be spent on expanding capacities for advanced technologies, such as 3nm, 4nm/5nm, and 6nm/7nm. Meanwhile, TSMC said that 10% of its CapEx will be allocated for advanced packaging and mask making, whereas another 10% will be spent on specialty technologies (which includes tailored versions of mature nodes).
In the coming weeks TSMC is set to start making chips using a performance-enhanced version of its N5 technology called N5P that promises to increase frequencies by up to 5% or reduce power consumption by up to 10% (at the same complexity). TSMC's N5 family of technologies also includes evolutionary N4 process that will enter risk production later this year and will be used for mass production in 2022. By the time N4 enters HVM in 2022, TSMC will have about two years of experience with N5 and three years of experience with EUV. So expectations are that yields will be high and the performance variability promises to be low.
In 2022, the world's largest contract maker of chips will roll out its brand-new N3 manufacturing process, which will keep using FinFET transistors, but is expected to offer the whole package of PPA improvements. In particular, versus their current N5 process, TSMC's N3 promises to increase performance by 10% – 15% (at the same power and complexity) or reduce power consumption by 25% – 30% (at the same performance and complexity). N3 will further increase the number of EUV layers, but will keep using DUV lithography. Also, since the technology keeps using FinFET, it will not require a new generation of electronic design automation (EDA) tools redesigned from scratch and development of all-new IPs, which might become a competitive advantage over Samsung Foundry's GAAFET/MBCFET-based 3GAE.
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Izvor: AnandTech
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Zadnje izmijenjeno od: The Exiled. 27.04.2021. u 11:09.
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