16.10.2020., 18:45
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#8643
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McG
Datum registracije: Feb 2014
Lokacija: Varaždin
Postovi: 8,060
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AMD Zen 3: An AnandTech Interview with CTO Mark Papermaster
Citiraj:
- Speaking to that process node, TSMC’s 7nm as you said: we’ve specifically been told that it is this sort of minor process update that was used for Ryzen 3000XT.
Are there any additional benefits that Ryzen 5000 is getting through the manufacturing process that perhaps we are not aware of?
Citiraj:
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It is in fact the core is in the same 7nm node, meaning that the process design kit [the PDK] is the same. So if you look at the transistors, they have the same design guidelines from the fab. What happens of course in any semiconductor fabrication node is that they are able to make adjustments in the manufacturing process so that of course is what they’ve done, for yield improvements and such. For every quarter, the process variation is reduced over time. When you hear ‘minor variations’ of 7nm, that is what is being referred to.
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- It’s funny you mention competitors, because recently they announced that they are moving to a very IP-block chiplet design scaling as appropriate.
This means chiplets for cores, for graphics, for security, for IO - exactly how far down the chiplet rabbit hole to we go here?
Citiraj:
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There is always a balance - a great idea overused can become a bad idea. It’s really based on each implementation. Everyone in the industry is going to have to find their sweet spot. Of course, there is supply chain complexity that has to be managed - so every design that we do at AMD, we’re focused on how do we get the best performance in the best organization physically, how we implement that performance, and ensure that we can deliver it through our supply chain reliably to our customers. That’s the tradeoff that we make for each and every product architecture.
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Izvor: AnandTech
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