[Manuel Calavera]

“This is an expected result. Client workloads do very little pure writing, so the CCD/IOD link is 32B/cycle while reading and 16B/cycle for writing. This allowed us to save power and area inside the package to spend on other, more beneficial areas for tangible performance benefits.”

In short, the pathway from the chiplet to the memory controller for the write data has been cut in half. This explains why it wasn’t noticeable when testing the Ryzen 9 3900X since it has two pathways to the controller, one from each chiplet so the results appeared normal. It was apparent from all the testing that this decision on the part of AMD had no noticeable effect on expected performance.