[McG]

Advanced Micro Devices on Wednesday displayed a die-shot of the forthcoming central processing unit (CPU) code-named Orochi, which is based on the Bulldozer micro-architecture and will be made using 32nm silicon-on-insulator process technology. The chip will feature eight processing engines, but since it is based on Bulldozer micro-architecture, those cores will be packed into four modules. Every module which will have two independent integer cores (that will share fetch, decode and L2 functionality) with dedicated schedulers, one floating point unit with two 128-bit FMAC pipes with one FP scheduler. The chip will have shared L3 cache, dual-channel DDR3 memory controller and will use HyperTransport 3.1 bus. The Orochi chips will use new AM3+ form-factor and will require brand new platforms.

The image clearly depicts four separate dual-core Bulldozer modules with unified level-two caches, various interfaces (memory, HyperTransport, etc.), rather strangely aligned level-three cache and so on. Besides design and instruction set improvements, Bulldozer, just like the code-named Llano accelerated processing unit (APU), supports advanced power management featuring chip power gating and digital measurements of temperatures. Obviously, the chip will be able to dynamically boost clock-speed when thermal design power allows and multiple cores are not required.

Izvor: X-bit Labs