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AMD has given us here at the AMDZone an unprecedented first look at the upcoming Bulldozer core, answering a lot of the miss information of there on the net today about the upcoming core. AMD was gracious enough to provide us with test boxes of the upcoming system, the chips are the Bulldozer A6 Stepping. One big feature, which improves performance a lot, is the ability to clock units at different clock frequencies (provided by flexible and efficient clock generators), to power off any idle subunit and to adapt sizes of caches, TLBs and some buffers and queues according to the needs of the executed code.

A power controller keeps track of load and power consumption of each of the many subunits and adapts clocks and units as needed. Further it increases throughput and power consumption of heavily loaded units as long as the processor doesn't exceed it's power consumption and temperature limits. If core 0 has not that many memory operations (less pressure on cache), the cache might be downsized to 8kB, 2-way by switching off 2 of the 4 ways it has. This way the power, the processor is allowed to use, will be directed to where it is needed and not to drive idle units. This is called Application Power Management as you might heard in some rumors on the net.

• L0 cache: 4 kB (8-way associative) trace cache for each thread (or core)
• L1 cache: 16 kB (4-way) data cache per core 1 cycle latency and 128 kB (4-way) instruction cache per module
• L2 cache: 2 MB (8-way) per module (shared between two cores), full-speed
• L3 cache: 8 MB shared between all cores, the L3 cache with a latency of 24 cycles will be able to serve up to 2 requests per (NB) clock cycle simultaneously and transfer data with 16B/clock to each of the reciepients.
• L4 cache: AMD has also announced that all Black Editions and Opterons models will come with 32/64MB L4 cache made possible through chip stacking.But now a bit more about the details. The instruction fetch unit (IFU) fetches code from the L1 instruction cache (at 32 Bytes/cycle)

One thing that has been confirmed is that the Bulldozer core has been shown to be incredibly resilient during early manufacturing samples, so much so that AMD has told us that it is experimenting using the 28nm bulk silicon process with only small changes to the die. Although AMD has not confirmed that they will use half stepping, they didn’t deny it either. One of the first things that AMD confirmed for us was that the upcoming AM3+ will be the last of the pin grid array (PGA) and that all upcoming processor would be land grid array (LGA) more on that later. The current AM3 Phenom II only use 938 pins, the upcoming Bulldozer and Bobcat cores will use all 941 pins. One of the benifiets of the AM3+ is that all AMD chips will be able to use DDR3 1866 (PC3 -15000) for staggering 60000MB/s as well as having advanced powersavings.

Going forward AMD’s will implement AMD’s Future socket or AMD’s Fusion socket, (Socket AF1) a massive Socket 1591 pins sock that will be the first of AMD’s next generation sock supporting DisplayPort 1.2, Full PCI Express 3.0 32 lane, and the addition of two more DDR channels allowing for quad channel memory. The Bulldozer design offers two levels to dynamical adjust the power and subsequently increase the power and frequency of the remaining active cores. The processors will automatically disable the second idle core in the module and. It is activated when the operating system requests the highest performance state of the processor. The technology is completely hardware-based, and will work transparently on any operating system.

As you have seen AMD if firing on all cylinders. Not only are they dominating the field if just about every benchmark. If this is just a preview release and the final silicone is yet to be case the future does indeed look much brighter for AMD. Unfortunately we were not able to procure Intel fancy new Core i7 980X. Maybe with a site name AMDZone, they are scared that we would give a biased review, who can blame them? However with the trouncing that the Bulldozer is giving the i7 975 two extra cores / four threads won’t make much of a difference.

Izvor: AMDZone